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c9678850bd
The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK pad for the PHY and the same 50 MHz clock are fed back to ETHRX via internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad using external pad-to-pad connection. Option (1) has two downsides. ETHCK_K is supplied directly from either PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and since the same PLL output is also used to supply SDMMC blocks, the performance of SD and eMMC access is affected. The second downside is that using this option, the EMI of the SoM is higher. Option (2) solves both of those problems, so implement it here. In this case, the PLL4_P is no longer limited and can be operated faster, at 100 MHz, which improves SDMMC performance (read performance is improved from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M count=1). The EMI interference also decreases. Ported from Linux kernel commit 73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
544 lines
11 KiB
Text
544 lines
11 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
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*/
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxaa-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/mfd/st,stpmic1.h>
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/ {
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aliases {
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ethernet0 = ðernet0;
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ethernet1 = &ksz8851;
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rtc0 = &hwrtc;
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rtc1 = &rtc;
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};
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memory@c0000000 {
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device_type = "memory";
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reg = <0xC0000000 0x40000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mcuram2: mcuram2@10000000 {
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compatible = "shared-dma-pool";
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reg = <0x10000000 0x40000>;
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no-map;
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};
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vdev0vring0: vdev0vring0@10040000 {
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compatible = "shared-dma-pool";
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reg = <0x10040000 0x1000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@10041000 {
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compatible = "shared-dma-pool";
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reg = <0x10041000 0x1000>;
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no-map;
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};
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vdev0buffer: vdev0buffer@10042000 {
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compatible = "shared-dma-pool";
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reg = <0x10042000 0x4000>;
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no-map;
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};
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mcuram: mcuram@30000000 {
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compatible = "shared-dma-pool";
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reg = <0x30000000 0x40000>;
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no-map;
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};
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retram: retram@38000000 {
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compatible = "shared-dma-pool";
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reg = <0x38000000 0x10000>;
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no-map;
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};
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};
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ethernet_vio: vioregulator {
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compatible = "regulator-fixed";
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regulator-name = "vio";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vdd>;
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};
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};
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&adc {
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vdd-supply = <&vdd>;
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vdda-supply = <&vdda>;
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vref-supply = <&vdda>;
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status = "okay";
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adc1: adc@0 {
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st,min-sample-time-nsecs = <5000>;
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st,adc-channels = <0>;
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status = "okay";
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};
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adc2: adc@100 {
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st,adc-channels = <1>;
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st,min-sample-time-nsecs = <5000>;
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status = "okay";
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};
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};
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&crc1 {
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status = "okay";
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};
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&dac {
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pinctrl-names = "default";
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pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
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vref-supply = <&vdda>;
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status = "okay";
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dac1: dac@1 {
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status = "okay";
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};
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dac2: dac@2 {
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status = "okay";
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};
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};
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&dts {
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status = "okay";
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};
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ðernet0 {
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status = "okay";
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pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>;
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pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
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pinctrl-names = "default", "sleep";
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phy-mode = "rmii";
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max-speed = <100>;
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phy-handle = <&phy0>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@1 {
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reg = <1>;
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/* LAN8710Ai */
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compatible = "ethernet-phy-id0007.c0f0",
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"ethernet-phy-ieee802.3-c22";
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clocks = <&rcc CK_MCO2>;
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reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500>;
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reset-deassert-us = <500>;
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smsc,disable-energy-detect;
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interrupt-parent = <&gpioi>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&fmc {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&fmc_pins_b>;
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pinctrl-1 = <&fmc_sleep_pins_b>;
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status = "okay";
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ksz8851: ethernet@1,0 {
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compatible = "micrel,ks8851-mll";
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reg = <1 0x0 0x2>, <1 0x2 0x20000>;
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interrupt-parent = <&gpioc>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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bank-width = <2>;
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/* Timing values are in nS */
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st,fmc2-ebi-cs-mux-enable;
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st,fmc2-ebi-cs-transaction-type = <4>;
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st,fmc2-ebi-cs-buswidth = <16>;
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st,fmc2-ebi-cs-address-setup-ns = <5>;
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st,fmc2-ebi-cs-address-hold-ns = <5>;
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st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
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st,fmc2-ebi-cs-data-setup-ns = <45>;
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st,fmc2-ebi-cs-data-hold-ns = <1>;
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st,fmc2-ebi-cs-write-address-setup-ns = <5>;
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st,fmc2-ebi-cs-write-address-hold-ns = <5>;
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st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
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st,fmc2-ebi-cs-write-data-setup-ns = <45>;
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st,fmc2-ebi-cs-write-data-hold-ns = <1>;
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};
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};
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&gpioa {
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-K", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpiob {
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gpio-line-names = "", "", "", "",
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"", "", "", "",
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"DHCOM-Q", "", "", "",
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"", "", "", "";
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};
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&gpioc {
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-E", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpiod {
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-B", "",
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"", "", "", "DHCOM-F",
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"DHCOM-D", "", "", "";
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};
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&gpioe {
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-P", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpiof {
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gpio-line-names = "", "", "", "DHCOM-A",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpiog {
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gpio-line-names = "DHCOM-C", "", "", "",
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"", "", "", "",
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"DHCOM-L", "", "", "",
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"", "", "", "";
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};
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&gpioh {
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gpio-line-names = "", "", "", "",
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"", "", "", "DHCOM-N",
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"DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U",
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"DHCOM-T", "", "DHCOM-S", "";
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};
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&gpioi {
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gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I",
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"DHCOM-R", "DHCOM-M", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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/* spare dmas for other usage */
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/delete-property/dmas;
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/delete-property/dma-names;
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hwrtc: rtc@32 {
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compatible = "microcrystal,rv8803";
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reg = <0x32>;
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};
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pmic: stpmic@33 {
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compatible = "st,stpmic1";
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reg = <0x33>;
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interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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regulators {
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compatible = "st,stpmic1-regulators";
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ldo1-supply = <&v3v3>;
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ldo2-supply = <&v3v3>;
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ldo3-supply = <&vdd_ddr>;
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ldo5-supply = <&v3v3>;
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ldo6-supply = <&v3v3>;
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pwr_sw1-supply = <&bst_out>;
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pwr_sw2-supply = <&bst_out>;
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vddcore: buck1 {
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regulator-name = "vddcore";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd_ddr: buck2 {
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regulator-name = "vdd_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd: buck3 {
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regulator-name = "vdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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st,mask-reset;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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v3v3: buck4 {
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-over-current-protection;
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regulator-initial-mode = <0>;
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};
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vdda: ldo1 {
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regulator-name = "vdda";
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regulator-always-on;
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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interrupts = <IT_CURLIM_LDO1 0>;
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};
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v2v8: ldo2 {
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regulator-name = "v2v8";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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interrupts = <IT_CURLIM_LDO2 0>;
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};
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vtt_ddr: ldo3 {
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regulator-name = "vtt_ddr";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <750000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd_usb: ldo4 {
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regulator-name = "vdd_usb";
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interrupts = <IT_CURLIM_LDO4 0>;
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};
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vdd_sd: ldo5 {
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regulator-name = "vdd_sd";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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interrupts = <IT_CURLIM_LDO5 0>;
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regulator-boot-on;
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};
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v1v8: ldo6 {
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regulator-name = "v1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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interrupts = <IT_CURLIM_LDO6 0>;
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};
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vref_ddr: vref_ddr {
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regulator-name = "vref_ddr";
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regulator-always-on;
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};
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bst_out: boost {
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regulator-name = "bst_out";
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interrupts = <IT_OCP_BOOST 0>;
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};
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vbus_otg: pwr_sw1 {
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regulator-name = "vbus_otg";
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interrupts = <IT_OCP_OTG 0>;
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};
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vbus_sw: pwr_sw2 {
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regulator-name = "vbus_sw";
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interrupts = <IT_OCP_SWOUT 0>;
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regulator-active-discharge = <1>;
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};
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};
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onkey {
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compatible = "st,stpmic1-onkey";
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interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
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interrupt-names = "onkey-falling", "onkey-rising";
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power-off-time-sec = <10>;
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status = "okay";
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};
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watchdog {
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compatible = "st,stpmic1-wdt";
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status = "disabled";
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};
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};
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touchscreen@49 {
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compatible = "ti,tsc2004";
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reg = <0x49>;
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vio-supply = <&v3v3>;
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interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>;
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};
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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&ipcc {
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status = "okay";
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};
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&iwdg2 {
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timeout-sec = <32>;
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status = "okay";
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};
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&m4_rproc {
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memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
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<&vdev0vring1>, <&vdev0buffer>;
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mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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mbox-names = "vq0", "vq1", "shutdown";
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interrupt-parent = <&exti>;
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interrupts = <68 1>;
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status = "okay";
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};
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&pwr_regulators {
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vdd-supply = <&vdd>;
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vdd_3v3_usbfs-supply = <&vdd_usb>;
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};
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&qspi {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qspi_clk_pins_a
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&qspi_bk1_pins_a
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&qspi_cs1_pins_a>;
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pinctrl-1 = <&qspi_clk_sleep_pins_a
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&qspi_bk1_sleep_pins_a
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&qspi_cs1_sleep_pins_a>;
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reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&rcc {
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/* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
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clocks = <&rcc CK_MCO2>;
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clock-names = "ETH_RX_CLK/ETH_REF_CLK";
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/*
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* Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
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* set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
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* so that MCO2 behaves as a divider for the ETHRX clock here.
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*/
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assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
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assigned-clock-parents = <&rcc PLL4_P>;
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assigned-clock-rates = <50000000>, <100000000>;
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};
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&rng1 {
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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&sdmmc1 {
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pinctrl-names = "default", "opendrain", "sleep", "init";
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pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
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pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
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pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
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pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>;
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cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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disable-wp;
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st,sig-dir;
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st,neg-edge;
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st,use-ckin;
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st,cmd-gpios = <&gpiod 2 0>;
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st,ck-gpios = <&gpioc 12 0>;
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st,ckin-gpios = <&gpioe 4 0>;
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bus-width = <4>;
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vmmc-supply = <&vdd_sd>;
|
|
status = "okay";
|
|
};
|
|
|
|
&sdmmc1_b4_pins_a {
|
|
/*
|
|
* SD bus pull-up resistors:
|
|
* - optional on SoMs with SD voltage translator
|
|
* - mandatory on SoMs without SD voltage translator
|
|
*/
|
|
pins1 {
|
|
bias-pull-up;
|
|
};
|
|
pins2 {
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
&sdmmc2 {
|
|
pinctrl-names = "default", "opendrain", "sleep";
|
|
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
|
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
|
|
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
|
|
non-removable;
|
|
no-sd;
|
|
no-sdio;
|
|
st,neg-edge;
|
|
bus-width = <8>;
|
|
vmmc-supply = <&v3v3>;
|
|
vqmmc-supply = <&v3v3>;
|
|
mmc-ddr-3_3v;
|
|
status = "okay";
|
|
};
|
|
|
|
&sdmmc3 {
|
|
pinctrl-names = "default", "opendrain", "sleep";
|
|
pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
|
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
|
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
|
broken-cd;
|
|
st,neg-edge;
|
|
bus-width = <4>;
|
|
vmmc-supply = <&v3v3>;
|
|
vqmmc-supply = <&v3v3>;
|
|
mmc-ddr-3_3v;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart4 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart4_pins_a>;
|
|
/delete-property/dmas;
|
|
/delete-property/dma-names;
|
|
status = "okay";
|
|
};
|