mirror of
https://github.com/AsahiLinux/u-boot
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b8bae824cc
Add support for the USB 3.0 devices in rk3588: - USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in rk3588s - USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in rk3588 only - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface as usbdp_phy0 - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface as usbdp_phy1 - USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0 mode - associated GRFs (general register files) for the devices. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> [eugen.hristev@collabora.com: move nodes to right place, adapt from latest linux kernel] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
100 lines
2.7 KiB
Text
100 lines
2.7 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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#include "rockchip-u-boot.dtsi"
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#include "rk3588s-u-boot.dtsi"
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/ {
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usbdrd3_1: usbdrd3_1 {
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compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
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clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
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<&cru ACLK_USB3OTG1>;
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clock-names = "ref", "suspend", "bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usbdrd_dwc3_1: usb@fc400000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfc400000 0x0 0x400000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
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power-domains = <&power RK3588_PD_USB>;
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resets = <&cru SRST_A_USB3OTG1>;
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reset-names = "usb3-otg";
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dr_mode = "host";
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phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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};
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};
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usbdpphy1_grf: syscon@fd5cc000 {
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compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
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reg = <0x0 0xfd5cc000 0x0 0x4000>;
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};
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usb2phy1_grf: syscon@fd5d4000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfd5d4000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy1: usb2-phy@4000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0x4000 0x10>;
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interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
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resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
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reset-names = "phy", "apb";
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy1";
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#clock-cells = <0>;
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rockchip,usbctrl-grf = <&usb_grf>;
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status = "disabled";
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u2phy1_otg: otg-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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usbdp_phy1: phy@fed90000 {
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compatible = "rockchip,rk3588-usbdp-phy";
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reg = <0x0 0xfed90000 0x0 0x10000>;
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rockchip,u2phy-grf = <&usb2phy1_grf>;
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rockchip,usb-grf = <&usb_grf>;
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rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
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rockchip,vo-grf = <&vo0_grf>;
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clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
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<&cru CLK_USBDP_PHY1_IMMORTAL>,
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<&cru PCLK_USBDPPHY1>,
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<&u2phy1>;
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clock-names = "refclk", "immortal", "pclk", "utmi";
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resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
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<&cru SRST_USBDP_COMBO_PHY1_CMN>,
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<&cru SRST_USBDP_COMBO_PHY1_LANE>,
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<&cru SRST_USBDP_COMBO_PHY1_PCS>,
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<&cru SRST_P_USBDPPHY1>;
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reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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status = "disabled";
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usbdp_phy1_dp: dp-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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usbdp_phy1_u3: usb3-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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