mirror of
https://github.com/AsahiLinux/u-boot
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1f54f71b18
Radxa E25 is a network application carrier board for the Radxa CM3I SoM with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key, USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header. Features tested on a Radxa E25 v1.4: - SD-card boot - eMMC boot - USB host - PCIe/Ethernet adapters is detected - SATA Device tree is imported from linux next-20230728. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: FUKAUMI Naoki <naoki@radxa.com>
236 lines
4.7 KiB
Text
236 lines
4.7 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include "rk3568-radxa-cm3i.dtsi"
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/ {
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model = "Radxa E25 Carrier Board";
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compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
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aliases {
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mmc1 = &sdmmc0;
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};
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pwm-leds {
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compatible = "pwm-leds-multicolor";
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multi-led {
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color = <LED_COLOR_ID_RGB>;
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max-brightness = <255>;
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led-red {
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color = <LED_COLOR_ID_RED>;
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pwms = <&pwm1 0 1000000 0>;
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};
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led-green {
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color = <LED_COLOR_ID_GREEN>;
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pwms = <&pwm2 0 1000000 0>;
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};
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led-blue {
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color = <LED_COLOR_ID_BLUE>;
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pwms = <&pwm12 0 1000000 0>;
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};
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};
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};
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vbus_typec: vbus-typec-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vbus_typec_en>;
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regulator-name = "vbus_typec";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc5v0_sys>;
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};
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/* actually fed by vcc5v0_sys, dependent
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* on pi6c clock generator
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*/
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vcc3v3_minipcie: vcc3v3-minipcie-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&minipcie_enable_h>;
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regulator-name = "vcc3v3_minipcie";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc3v3_pi6c_05>;
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};
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vcc3v3_ngff: vcc3v3-ngff-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&ngffpcie_enable_h>;
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regulator-name = "vcc3v3_ngff";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc5v0_sys>;
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};
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vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie30x1_enable_h>;
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regulator-name = "vcc3v3_pcie30x1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc5v0_sys>;
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};
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vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_enable_h>;
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regulator-name = "vcc3v3_pcie";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc5v0_sys>;
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};
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};
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&combphy1 {
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phy-supply = <&vcc3v3_pcie30x1>;
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};
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&pcie2x1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie20_reset_h>;
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reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pi6c_05>;
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status = "okay";
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};
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&pcie30phy {
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data-lanes = <1 2>;
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status = "okay";
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};
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&pcie3x1 {
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num-lanes = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie30x1m0_pins>;
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reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_minipcie>;
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status = "okay";
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};
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&pcie3x2 {
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num-lanes = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie30x2_reset_h>;
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reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pi6c_05>;
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status = "okay";
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};
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&pinctrl {
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pcie {
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pcie20_reset_h: pcie20-reset-h {
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rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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pcie30x1_enable_h: pcie30x1-enable-h {
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rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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pcie30x2_reset_h: pcie30x2-reset-h {
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rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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pcie_enable_h: pcie-enable-h {
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rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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usb {
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minipcie_enable_h: minipcie-enable-h {
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rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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ngffpcie_enable_h: ngffpcie-enable-h {
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rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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vbus_typec_en: vbus_typec_en {
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rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pwm1 {
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status = "okay";
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};
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&pwm2 {
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status = "okay";
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};
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&pwm12 {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm12m1_pins>;
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status = "okay";
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};
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&sata1 {
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status = "okay";
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};
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&sdmmc0 {
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bus-width = <4>;
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cap-sd-highspeed;
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cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
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/* Also used in pcie30x1_clkreqnm0 */
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc3v3_sd>;
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vqmmc-supply = <&vccio_sd>;
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status = "okay";
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};
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&usb_host0_ehci {
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status = "okay";
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};
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&usb_host0_ohci {
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status = "okay";
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};
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&usb_host0_xhci {
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status = "okay";
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};
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&usb_host1_ehci {
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status = "okay";
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};
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&usb_host1_ohci {
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status = "okay";
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};
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&usb2phy0_otg {
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phy-supply = <&vbus_typec>;
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status = "okay";
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};
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&usb2phy1_host {
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phy-supply = <&vcc3v3_minipcie>;
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status = "okay";
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};
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&usb2phy1_otg {
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phy-supply = <&vcc3v3_ngff>;
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status = "okay";
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};
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