u-boot/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
Neha Malcom Francis 177178685a j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img
By providing entries in the binman node of the device tree, binman will
be able to find and package board config artifacts generated by
TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.
It will also pick out the R5 SPL and sign it with the help of TI signing
entry and generate the final tiboot3.bin.

Entries for A72 build have been added to k3-j721e-binman.dtsi to
generate tispl.bin and u-boot.img.

Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images
In HS-SE, the encrypted system firmware binary must be signed along with
the signed certificate binary.

HS-SE:
	* tiboot3-j721e_sr1_1-hs-evm.bin
	* sysfw-j721e_sr1_1-hs-evm.itb
	* tispl.bin
	* u-boot.img

HS-FS:
	* tiboot3-j721e_sr2-hs-fs-evm.bin
	* sysfw-j721e_sr2-hs-fs-evm.itb
	* tispl.bin
	* u-boot.img

GP:
	* tiboot3.bin -->tiboot3-j721e-gp-evm.bin
	* sysfw.itb --> sysfw-j721e-gp-evm.itb
	* tispl.bin_unsigned
	* u-boot.img_unsigned

It is to be noted that the bootflow followed by J721E requires:

tiboot3.bin:
	* R5 SPL
	* R5 SPL dtbs

sysfw.itb:
	* TIFS
	* board-cfg
	* pm-cfg
	* sec-cfg
	* rm-cfg

tispl.bin:
	* DM
	* ATF
	* OP-TEE
	* A72 SPL
	* A72 SPL dtbs

u-boot.img:
	* A72 U-Boot
	* A72 U-Boot dtbs

Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:58 -04:00

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4.1 KiB
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-j721e-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
aliases {
ethernet0 = &cpsw_port1;
spi0 = &ospi0;
spi1 = &ospi1;
remoteproc0 = &mcu_r5fss0_core0;
remoteproc1 = &mcu_r5fss0_core1;
remoteproc2 = &main_r5fss0_core0;
remoteproc3 = &main_r5fss0_core1;
remoteproc4 = &main_r5fss1_core0;
remoteproc5 = &main_r5fss1_core1;
remoteproc6 = &c66_0;
remoteproc7 = &c66_1;
remoteproc8 = &c71_0;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &mcu_i2c1;
i2c3 = &main_i2c0;
};
};
&cbass_main{
bootph-pre-ram;
main_navss: bus@30000000 {
bootph-pre-ram;
};
};
&cbass_mcu_wakeup {
bootph-pre-ram;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <250000000>;
bootph-pre-ram;
};
mcu_navss: bus@28380000 {
bootph-pre-ram;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
bootph-pre-ram;
};
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
bootph-pre-ram;
};
};
chipid@43000014 {
bootph-pre-ram;
};
};
&secure_proxy_main {
bootph-pre-ram;
};
&dmsc {
bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
};
};
&k3_pds {
bootph-pre-ram;
};
&k3_clks {
bootph-pre-ram;
};
&k3_reset {
bootph-pre-ram;
};
&wkup_pmx0 {
bootph-pre-ram;
};
&main_pmx0 {
bootph-pre-ram;
};
&main_uart0 {
bootph-pre-ram;
};
&mcu_uart0 {
bootph-pre-ram;
};
&main_sdhci0 {
bootph-pre-ram;
};
&main_sdhci1 {
bootph-pre-ram;
};
&wiz3_pll1_refclk {
assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
};
&main_usbss0_pins_default {
bootph-pre-ram;
};
&usbss0 {
bootph-pre-ram;
};
&usb0 {
dr_mode = "peripheral";
bootph-pre-ram;
};
&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x2>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
cpsw-phy-sel@40f04040 {
compatible = "ti,am654-cpsw-phy-sel";
reg= <0x0 0x40f04040 0x0 0x4>;
reg-names = "gmii-sel";
};
};
&main_mmc1_pins_default {
bootph-pre-ram;
};
&wkup_i2c0_pins_default {
bootph-pre-ram;
};
&wkup_i2c0 {
bootph-pre-ram;
};
&main_i2c0 {
bootph-pre-ram;
};
&main_i2c0_pins_default {
bootph-pre-ram;
};
&exp2 {
bootph-pre-ram;
};
&mcu_fss0_ospi0_pins_default {
bootph-pre-ram;
};
&fss {
bootph-pre-ram;
};
&hbmc {
bootph-pre-ram;
flash@0,0 {
bootph-pre-ram;
};
};
&hbmc_mux {
bootph-pre-ram;
};
&wkup_gpio0 {
bootph-pre-ram;
};
&ospi0 {
bootph-pre-ram;
flash@0 {
bootph-pre-ram;
};
};
&ospi1 {
bootph-pre-ram;
flash@0 {
bootph-pre-ram;
};
};
&mcu_fss0_hpb0_pins_default {
bootph-pre-ram;
};
&wkup_gpio_pins_default {
bootph-pre-ram;
};
&mcu_fss0_ospi1_pins_default {
bootph-pre-ram;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};
&main_r5fss1 {
ti,cluster-mode = <0>;
};
&wiz3_pll1_refclk {
assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
};
&serdes_ln_ctrl {
u-boot,mux-autoprobe;
};
&usb_serdes_mux {
u-boot,mux-autoprobe;
};
&serdes0 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&serdes0_pcie_link {
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz0_pll1_refclk>;
};
&serdes0_qsgmii_link {
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
assigned-clock-parents = <&wiz0_pll1_refclk>;
};