mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
77c29cb1b6
Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images. HS-SE: * tiboot3-am65x_sr2-hs-evm.bin * sysfw-am65x_sr2-hs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin * sysfw.itb --> sysfw-am65x_sr2-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM65x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
208 lines
3.1 KiB
Text
208 lines
3.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include "k3-am65x-binman.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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};
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aliases {
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serial2 = &main_uart0;
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ethernet0 = &cpsw_port1;
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usb0 = &usb0;
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usb1 = &usb1;
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spi0 = &ospi0;
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spi1 = &ospi1;
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};
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};
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&cbass_main{
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bootph-pre-ram;
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main_navss: bus@30800000 {
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bootph-pre-ram;
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};
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};
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&cbass_mcu {
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bootph-pre-ram;
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mcu_navss: bus@28380000 {
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bootph-pre-ram;
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ringacc@2b800000 {
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>,
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<0x0 0x28440000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
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bootph-pre-ram;
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ti,dma-ring-reset-quirk;
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};
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dma-controller@285c0000 {
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x284c0000 0x0 0x4000>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x284a0000 0x0 0x4000>,
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<0x0 0x2aa00000 0x0 0x40000>,
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<0x0 0x28400000 0x0 0x2000>;
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reg-names = "gcfg", "rchan", "rchanrt", "tchan",
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"tchanrt", "rflow";
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bootph-pre-ram;
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};
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};
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};
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&cbass_wakeup {
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bootph-pre-ram;
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chipid@43000014 {
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bootph-pre-ram;
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};
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};
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&secure_proxy_main {
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bootph-pre-ram;
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};
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&dmsc {
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bootph-pre-ram;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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bootph-pre-ram;
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};
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};
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&k3_pds {
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bootph-pre-ram;
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};
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&k3_clks {
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bootph-pre-ram;
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};
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&k3_reset {
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bootph-pre-ram;
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};
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&wkup_pmx0 {
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bootph-pre-ram;
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wkup_i2c0_pins_default {
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bootph-pre-ram;
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};
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};
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&main_pmx0 {
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bootph-pre-ram;
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usb0_pins_default: usb0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
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>;
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bootph-pre-ram;
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};
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};
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&main_uart0_pins_default {
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bootph-pre-ram;
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};
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&main_pmx1 {
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bootph-pre-ram;
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};
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&wkup_pmx0 {
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mcu-fss0-ospi0-pins-default {
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bootph-pre-ram;
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};
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};
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&main_uart0 {
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bootph-pre-ram;
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};
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&main_mmc0_pins_default {
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bootph-pre-ram;
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};
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&main_mmc1_pins_default {
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bootph-pre-ram;
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};
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&sdhci0 {
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bootph-pre-ram;
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};
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&sdhci1 {
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bootph-pre-ram;
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};
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&davinci_mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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&mcu_cpsw {
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reg = <0x0 0x46000000 0x0 0x200000>,
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<0x0 0x40f00200 0x0 0x2>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@40f04040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg= <0x0 0x40f04040 0x0 0x4>;
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reg-names = "gmii-sel";
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};
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};
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&wkup_i2c0 {
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bootph-pre-ram;
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};
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&usb1 {
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dr_mode = "peripheral";
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};
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&fss {
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bootph-pre-ram;
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};
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&ospi0 {
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bootph-pre-ram;
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flash@0{
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bootph-pre-ram;
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};
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};
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&dwc3_0 {
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status = "okay";
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bootph-pre-ram;
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};
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&usb0_phy {
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status = "okay";
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bootph-pre-ram;
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};
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&usb0 {
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pinctrl-names = "default";
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pinctrl-0 = <&usb0_pins_default>;
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dr_mode = "peripheral";
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bootph-pre-ram;
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};
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&scm_conf {
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bootph-pre-ram;
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};
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