mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
7937af120b
Update the am62 and am625 device-trees from linux v6.5-rc1. This needed the following tweaks to the u-boot specific dtsi as well: - Switch tick-timer to the main_timer as it's now defined in the main dtsi - Secure proxies are defined in SoC dtsi - Drop duplicate nodes - u-boot.dtsi is includes in r5-sk, no need for either the definitions from main.dtsi OR duplication from u-boot.dtsi Reviewed-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Maxime Ripard <mripard@kernel.org> Tested-by: Maxime Ripard <mripard@kernel.org> Cc: Francesco Dolcini <francesco@dolcini.it> Cc: Sjoerd Simons <sjoerd@collabora.com> Cc: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Nishanth Menon <nm@ti.com>
131 lines
1.3 KiB
Text
131 lines
1.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Common AM625 SK dts file for SPLs
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* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "k3-am625-sk-binman.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &main_timer0;
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};
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aliases {
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mmc1 = &sdhci1;
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};
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memory@80000000 {
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bootph-pre-ram;
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};
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};
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&cbass_main {
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bootph-pre-ram;
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};
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&main_timer0 {
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clock-frequency = <25000000>;
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bootph-pre-ram;
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};
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&dmss {
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bootph-pre-ram;
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};
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&secure_proxy_main {
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bootph-pre-ram;
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};
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&dmsc {
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bootph-pre-ram;
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};
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&k3_pds {
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bootph-pre-ram;
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};
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&k3_clks {
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bootph-pre-ram;
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};
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&k3_reset {
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bootph-pre-ram;
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};
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&wkup_conf {
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bootph-pre-ram;
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};
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&chipid {
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bootph-pre-ram;
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};
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&main_pmx0 {
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bootph-pre-ram;
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};
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&main_uart0 {
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bootph-pre-ram;
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};
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&main_uart0_pins_default {
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bootph-pre-ram;
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};
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&cbass_mcu {
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bootph-pre-ram;
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};
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&cbass_wakeup {
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bootph-pre-ram;
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};
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&mcu_pmx0 {
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bootph-pre-ram;
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};
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&sdhci1 {
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bootph-pre-ram;
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};
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&main_mmc1_pins_default {
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bootph-pre-ram;
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};
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&fss {
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bootph-pre-ram;
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};
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&ospi0_pins_default {
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bootph-pre-ram;
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};
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&ospi0 {
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bootph-pre-ram;
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flash@0 {
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bootph-pre-ram;
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partitions {
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bootph-pre-ram;
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partition@3fc0000 {
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bootph-pre-ram;
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};
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};
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};
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};
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&cpsw3g {
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bootph-pre-ram;
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};
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&cpsw_port1 {
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bootph-pre-ram;
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};
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&cpsw_port2 {
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status = "disabled";
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};
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