mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 11:00:15 +00:00
3bc6257e80
Add i.MX8QM DMSSE20 a1 board support U-Boot 2023.04-00030-g7be2f547b2 (Apr 21 2023 - 11:11:43 +0200) Model: Advantech iMX8QM DMSSE20 Board: DMS-SE20A1 8GB Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363 Boot: USB DRAM: 8 GiB Core: 100 devices, 19 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: eth0: ethernet@5b040000 Warning: ethernet@5b050000 (eth1) using random MAC address - 32:05:0c:f9:5e:10 , eth1: ethernet@5b050000 Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
397 lines
11 KiB
Text
397 lines
11 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2017-2018 NXP
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* Copyright 2019-2023 Kococonnector GmbH
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*/
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/dts-v1/;
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/* First 128KB is for PSCI ATF. */
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/memreserve/ 0x80000000 0x00020000;
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#include "fsl-imx8qm.dtsi"
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#include "imx8qm-u-boot.dtsi"
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/ {
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model = "Advantech iMX8QM DMSSE20";
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compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
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aliases {
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mmc0 = &usdhc1;
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mmc2 = &usdhc3;
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};
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon";
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stdout-path = &lpuart0;
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};
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reg_usb_otg1_vbus: usb_otg1_vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx8qm-mek {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
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SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020
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SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020
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SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
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SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
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SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
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SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
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SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
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SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
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SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
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SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
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SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
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SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
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SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
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SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
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SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
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>;
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};
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pinctrl_lpi2c2: lpi2c2grp {
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fsl,pins = <
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SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c
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SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_DMA_UART0_RX 0x06000020
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SC_P_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_rtc_mc_8803: rtc-mc-8803-grp{
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fsl,pins = <
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SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c
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SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020
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SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020
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>;
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};
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pinctrl_usdhc3_gpio: usdhc3grpgpio {
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fsl,pins = <
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SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
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SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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>;
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};
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};
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};
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&gpio2 {
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status = "okay";
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};
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&gpio4 {
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status = "okay";
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};
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&gpio5 {
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status = "okay";
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};
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&usdhc1 {
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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status = "okay";
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};
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&usdhc2 {
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bus-width = <4>;
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cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&usdhc3 {
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bus-width = <4>;
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cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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pinctrl-names = "default","state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
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wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&fec1 {
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fsl,ar8031-phy-fixup;
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fsl,magic-packet;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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};
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};
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};
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&fec2 {
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fsl,ar8031-phy-fixup;
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fsl,magic-packet;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec2>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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};
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};
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};
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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status = "okay";
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};
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&i2c2 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c2>;
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status = "okay";
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};
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&i2c3 {
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#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_rtc_mc_8803>;
|
|
status = "okay";
|
|
|
|
rv8803@32 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "microcrystal,rv8803";
|
|
reg = <0x32>;
|
|
};
|
|
|
|
24c02@50 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,24c04";
|
|
reg = <0x50>;
|
|
};
|
|
};
|
|
|
|
&lpuart0 { /* console */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_lpuart0>;
|
|
status = "okay";
|
|
};
|