mirror of
https://github.com/AsahiLinux/u-boot
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181d1684ca
Synchronise device tree with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
613 lines
14 KiB
Text
613 lines
14 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree File for the Kontron pitx-imx8m board.
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*
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* Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
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*/
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/dts-v1/;
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#include "imx8mq.dtsi"
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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model = "Kontron pITX-imx8m";
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compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
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aliases {
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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spi0 = &qspi0;
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spi1 = &ecspi2;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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};
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pcie0_refclk: pcie0-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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pcie1_refclk: pcie1-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2>;
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regulator-name = "V_3V3_SD";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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off-on-delay-us = <20000>;
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enable-active-high;
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};
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};
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&ecspi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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tpm@0 {
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compatible = "infineon,slb9670";
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reg = <0>;
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spi-max-frequency = <43000000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10>;
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reset-deassert-us = <280>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@8 {
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compatible = "fsl,pfuze100";
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fsl,pfuze-support-disable-sw;
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reg = <0x8>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-name = "V_0V9_GPU";
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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};
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sw1c_reg: sw1c {
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regulator-name = "V_0V9_VPU";
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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};
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sw2_reg: sw2 {
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regulator-name = "V_1V1_NVCC_DRAM";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-name = "V_1V0_DRAM";
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-name = "V_1V8_S0";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-name = "NC";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-name = "V_0V9_SNVS";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-name = "V_0V55_VREF_DDR";
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-name = "V_1V5_CSI";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-name = "V_0V9_PHY";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <975000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-name = "V_1V8_PHY";
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regulator-min-microvolt = <1675000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-name = "V_1V8_VDDA";
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regulator-min-microvolt = <1625000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-name = "V_3V3_PHY";
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regulator-min-microvolt = <3075000>;
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regulator-max-microvolt = <3625000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-name = "V_2V8_CAM";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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fan-controller@1b {
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compatible = "maxim,max6650";
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reg = <0x1b>;
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maxim,fan-microvolt = <5000000>;
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};
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rtc@32 {
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compatible = "microcrystal,rv8803";
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reg = <0x32>;
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};
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sensor@4b {
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compatible = "national,lm75b";
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reg = <0x4b>;
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};
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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pagesize = <32>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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/* M.2 B-key slot */
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
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<&clk IMX8MQ_CLK_PCIE1_AUX>,
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<&clk IMX8MQ_CLK_PCIE1_PHY>,
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<&pcie0_refclk>;
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clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
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status = "okay";
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};
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/* Intel Ethernet Controller I210/I211 */
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&pcie1 {
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clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
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<&clk IMX8MQ_CLK_PCIE2_AUX>,
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<&clk IMX8MQ_CLK_PCIE2_PHY>,
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<&pcie1_refclk>;
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clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
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fsl,max-link-speed = <1>;
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status = "okay";
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};
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&pgc_gpu {
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power-supply = <&sw1a_reg>;
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};
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&pgc_vpu {
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power-supply = <&sw1c_reg>;
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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m25p,fast-read;
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spi-max-frequency = <50000000>;
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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uart-has-rtscts;
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assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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status = "okay";
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};
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&usb3_phy0 {
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&usb_dwc3_0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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maximum-speed = "high-speed";
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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vqmmc-supply = <&sw4_reg>;
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bus-width = <8>;
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non-removable;
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no-sd;
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no-sdio;
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
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MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
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>;
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};
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pinctrl_gpio: gpiogrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
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MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
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MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
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MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
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MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
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MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
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MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
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MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
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MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
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>;
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};
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pinctrl_reg_usdhc2: regusdhc2gpiogrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
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MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
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MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
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MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
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MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
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>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
|
|
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
|
|
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
|
|
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_ecspi2_cs: ecspi2csgrp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
|
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
|
|
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
|
|
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
|
|
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
|
|
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1-100grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1-200grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
|
|
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usb0: usb0grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
|
|
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
|
>;
|
|
};
|
|
};
|