mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 19:10:13 +00:00
c7ea9612df
The assigned-clock no longer have to be dropped, the clock are now defined in clk-imx8mp.c and used by DWMAC driver to configure the DWMAC clock. Drop the workarounds from U-Boot specific DT extras. Signed-off-by: Marek Vasut <marex@denx.de>
238 lines
3.2 KiB
Text
238 lines
3.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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bootph-pre-ram;
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wdt = <&wdog1>;
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};
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};
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ðphy0 {
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reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
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reset-delay-us = <1000>;
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reset-post-delay-us = <300000>;
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};
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&fec {
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phy-reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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&gpio1 {
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bootph-pre-ram;
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dio0_hog {
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gpio-hog;
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input;
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gpios = <9 GPIO_ACTIVE_LOW>;
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line-name = "dio0";
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};
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dio1_hog {
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gpio-hog;
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input;
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gpios = <11 GPIO_ACTIVE_LOW>;
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line-name = "dio1";
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};
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};
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&gpio2 {
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bootph-pre-ram;
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pcie1_wdis_hog {
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gpio-hog;
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gpios = <17 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "pcie1_wdis#";
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};
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pcie2_wdis_hog {
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gpio-hog;
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gpios = <18 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "pcie2_wdis#";
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};
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pcie3_wdis_hog {
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gpio-hog;
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gpios = <14 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "pcie3_wdis#";
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};
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};
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&gpio3 {
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bootph-pre-ram;
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m2_dis2_hog {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "m2_gdis#";
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};
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m2rst_hog {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "m2_rst#";
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};
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m2_off_hog {
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gpio-hog;
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gpios = <14 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "m2_off#";
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};
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};
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&gpio4 {
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bootph-pre-ram;
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m2_dis1_hog {
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gpio-hog;
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gpios = <18 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "m2_wdis#";
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};
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rs485_en {
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gpio-hog;
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gpios = <31 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "rs485_en";
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};
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};
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&gpio5 {
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bootph-pre-ram;
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rs485_half {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "rs485_hd";
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};
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rs485_term {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "rs485_term";
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};
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};
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&i2c1 {
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bootph-pre-ram;
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};
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&i2c2 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&pinctrl_i2c1 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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lan1: port@0 {
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phy-handle = <&sw_phy0>;
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};
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lan2: port@1 {
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phy-handle = <&sw_phy1>;
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};
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lan3: port@2 {
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phy-handle = <&sw_phy2>;
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};
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lan4: port@3 {
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phy-handle = <&sw_phy3>;
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};
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lan5: port@4 {
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phy-handle = <&sw_phy4>;
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};
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};
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mdios {
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0>;
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compatible = "microchip,ksz-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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sw_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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sw_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sw_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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sw_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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sw_phy4: ethernet-phy@4 {
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reg = <0x4>;
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};
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};
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};
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};
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&usdhc2 {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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assigned-clock-rates = <400000000>;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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bootph-pre-ram;
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};
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&usdhc3 {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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assigned-clock-rates = <400000000>;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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bootph-pre-ram;
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};
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&wdog1 {
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bootph-pre-ram;
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};
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