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https://github.com/AsahiLinux/u-boot
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d12618b927
Add the board support for the i.MX8MM Cloos PHG board. This board uses a imx8mm-tqma8mqml SoM from TQ-Group. imx8mm-phg.dts and imx8mm-tqma8mqml.dtsi are taken directly from Linux 6.2-rc3. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
266 lines
5.9 KiB
Text
266 lines
5.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Fabio Estevam <festevam@denx.de>
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*/
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/dts-v1/;
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#include "imx8mm-tqma8mqml.dtsi"
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/ {
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model = "Cloos i.MX8MM PHG board";
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compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
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aliases {
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mmc0 = &usdhc3;
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mmc1 = &usdhc2;
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};
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chosen {
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stdout-path = &uart2;
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};
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beeper {
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compatible = "gpio-beeper";
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pinctrl-0 = <&pinctrl_beeper>;
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gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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led-0 {
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label = "status1";
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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led-1 {
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label = "status2";
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gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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led-2 {
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label = "status3";
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gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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};
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led-3 {
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label = "run";
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gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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};
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led-4 {
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label = "powerled";
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gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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};
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};
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reg_usb_otg_vbus: regulator-usb-otg-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_otg_vbus_ctrl>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-vmmc {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usbphynop1 {
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power-domains = <&pgc_otg1>;
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};
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&usbphynop2 {
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power-domains = <&pgc_otg2>;
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};
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&usbotg1 {
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dr_mode = "host";
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vbus-supply = <®_usb_otg_vbus>;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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disable-wp;
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no-mmc;
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no-sdio;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_beeper: beepergrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
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MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
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MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
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MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002
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MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14
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MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14
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MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
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MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
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MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14
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MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14
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MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10
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>;
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};
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pinctrl_gpio_led: gpioledgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
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MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
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MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
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MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
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MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
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>;
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};
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};
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