mirror of
https://github.com/AsahiLinux/u-boot
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2f96d4dd95
Synchronise device tree with linux-next next-20220708. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
220 lines
5.7 KiB
Text
220 lines
5.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Copyright 2015 Freescale Semiconductor, Inc.
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// Copyright 2016 Toradex AG
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#include "imx7s.dtsi"
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#include <dt-bindings/reset/imx7-reset.h>
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/ {
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aliases {
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usb0 = &usbotg1;
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usb1 = &usbotg2;
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usb2 = &usbh;
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};
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cpus {
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cpu0: cpu@0 {
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clock-frequency = <996000000>;
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>;
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nvmem-cells = <&fuse_grade>;
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nvmem-cell-names = "speed_grade";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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clock-frequency = <996000000>;
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_sleep_wait>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-792000000 {
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opp-hz = /bits/ 64 <792000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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opp-supported-hw = <0xd>, <0x7>;
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opp-suspend;
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};
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opp-996000000 {
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opp-hz = /bits/ 64 <996000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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opp-supported-hw = <0xc>, <0x7>;
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opp-suspend;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1225000>;
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clock-latency-ns = <150000>;
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opp-supported-hw = <0x8>, <0x3>;
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opp-suspend;
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};
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};
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usbphynop2: usbphynop2 {
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compatible = "usb-nop-xceiv";
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clocks = <&clks IMX7D_USB_PHY2_CLK>;
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clock-names = "main_clk";
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#phy-cells = <0>;
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};
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soc: soc {
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etm@3007d000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x3007d000 0x1000>;
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/*
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* System will hang if added nosmp in kernel command line
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* without arm,primecell-periphid because amba bus try to
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* read id and core1 power off at this time.
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*/
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arm,primecell-periphid = <0xbb956>;
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cpu = <&cpu1>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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etm1_out_port: endpoint {
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remote-endpoint = <&ca_funnel_in_port1>;
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};
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};
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};
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};
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intc: interrupt-controller@31001000 {
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compatible = "arm,cortex-a7-gic";
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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reg = <0x31001000 0x1000>,
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<0x31002000 0x2000>,
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<0x31004000 0x2000>,
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<0x31006000 0x2000>;
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};
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pcie: pcie@33800000 {
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compatible = "fsl,imx7d-pcie";
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reg = <0x33800000 0x4000>,
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<0x4ff00000 0x80000>;
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reg-names = "dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */
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<0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
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num-lanes = <1>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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/*
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* Reference manual lists pci irqs incorrectly
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* Real hardware ordering is same as imx6: D+MSI, C, B, A
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*/
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interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
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<&clks IMX7D_PCIE_PHY_ROOT_CLK>;
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clock-names = "pcie", "pcie_bus", "pcie_phy";
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assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
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<&clks IMX7D_PCIE_PHY_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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fsl,max-link-speed = <2>;
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power-domains = <&pgc_pcie_phy>;
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resets = <&src IMX7_RESET_PCIEPHY>,
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<&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
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<&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
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reset-names = "pciephy", "apps", "turnoff";
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fsl,imx7d-pcie-phy = <&pcie_phy>;
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status = "disabled";
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};
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};
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};
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&aips2 {
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pcie_phy: pcie-phy@306d0000 {
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compatible = "fsl,imx7d-pcie-phy";
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reg = <0x306d0000 0x10000>;
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status = "disabled";
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};
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};
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&aips3 {
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usbotg2: usb@30b20000 {
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compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
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reg = <0x30b20000 0x200>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_USB_CTRL_CLK>;
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fsl,usbphy = <&usbphynop2>;
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fsl,usbmisc = <&usbmisc2 0>;
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phy-clkgate-delay-us = <400>;
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status = "disabled";
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};
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usbmisc2: usbmisc@30b20200 {
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#index-cells = <1>;
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compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
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reg = <0x30b20200 0x200>;
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};
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fec2: ethernet@30bf0000 {
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compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
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reg = <0x30bf0000 0x10000>;
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interrupt-names = "int0", "int1", "int2", "pps";
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
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<&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
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<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues = <3>;
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fsl,num-rx-queues = <3>;
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fsl,stop-mode = <&gpr 0x10 4>;
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status = "disabled";
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};
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};
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&ca_funnel_in_ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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ca_funnel_in_port1: endpoint {
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remote-endpoint = <&etm1_out_port>;
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};
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};
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};
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