mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
4ad2ff5166
Synchronise device tree with linux v6.0-rc1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
587 lines
13 KiB
Text
587 lines
13 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "imx6sx.dtsi"
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/ {
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model = "Softing VIN|ING 2000";
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compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
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chosen {
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stdout-path = &uart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_peri_3v3: regulator-peri_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "peri_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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led-controller {
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compatible = "pwm-leds";
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led-1 {
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label = "red";
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max-brightness = <255>;
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pwms = <&pwm6 0 50000>;
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};
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led-2 {
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label = "green";
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max-brightness = <255>;
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pwms = <&pwm2 0 50000>;
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};
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led-3 {
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label = "blue";
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max-brightness = <255>;
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pwms = <&pwm1 0 50000>;
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};
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};
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};
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&adc1 {
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vref-supply = <®_peri_3v3>;
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status = "okay";
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};
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&cpu0 {
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/*
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* This board has a shared rail of reg_arm and reg_soc (supplied by
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* sw1a_reg) which is modeled below, but still this module behaves
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* unstable without higher voltages. Hence, set higher voltages here.
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*/
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operating-points = <
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/* kHz uV */
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996000 1250000
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792000 1175000
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396000 1175000
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198000 1175000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC uV */
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996000 1250000
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792000 1175000
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396000 1175000
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198000 1175000
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>;
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};
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&ecspi4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi4>;
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cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-supply = <®_peri_3v3>;
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phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <5>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet0-phy@0 {
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reg = <0>;
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max-speed = <100>;
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interrupt-parent = <&gpio2>;
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-supply = <®_peri_3v3>;
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phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <5>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet1-phy@0 {
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reg = <0>;
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max-speed = <100>;
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interrupt-parent = <&gpio2>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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proximity: sx9500@28 {
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compatible = "semtech,sx9500";
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reg = <0x28>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sx9500>;
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interrupt-parent = <&gpio2>;
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interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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};
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pmic: pfuze100@8 {
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compatible = "fsl,pfuze200";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3a {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3b_reg: sw3b {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpios>;
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pinctrl_ecspi4: ecspi4grp {
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fsl,pins = <
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MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1
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MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1
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MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1
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MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1
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MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1
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MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9
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MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9
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MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1
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MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9
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MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038
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/* LAN8720 PHY Reset */
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MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0
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/* MDIO */
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MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9
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MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9
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/* IRQ from PHY */
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MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0
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MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0
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MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0
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MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0
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MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0
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MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0
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MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038
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/* LAN8720 PHY Reset */
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MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0
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/* MDIO */
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MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9
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MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9
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/* IRQ from PHY */
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MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
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MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
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MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
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>;
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};
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pinctrl_gpios: gpiosgrp {
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fsl,pins = <
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/* reset external uC */
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MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0
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/* IRQ from external uC */
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MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0
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/* overcurrent detection */
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MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
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MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1
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MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1
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>;
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};
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0
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>;
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};
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pinctrl_pwm1: pwm1grp-1 {
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fsl,pins = <
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/* blue LED */
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MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1
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>;
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};
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pinctrl_pwm2: pwm2grp-1 {
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fsl,pins = <
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/* green LED */
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MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1
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>;
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};
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pinctrl_pwm6: pwm6grp-1 {
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fsl,pins = <
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/* red LED */
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MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1
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>;
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};
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pinctrl_sx9500: sx9500grp {
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fsl,pins = <
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/* Reset */
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MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838
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/* IRQ */
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MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
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MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1
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MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usb_otg1: usbotg1grp {
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
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>;
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};
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pinctrl_usb_otg1_id: usbotg1idgrp {
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fsl,pins = <
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MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
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>;
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};
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pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
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fsl,pins = <
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MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
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MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
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MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
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MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
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MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
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MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
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MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000
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MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
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fsl,pins = <
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MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9
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MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9
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MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9
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MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9
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MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9
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MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
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fsl,pins = <
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MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9
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MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9
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MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9
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MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9
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MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9
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MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9
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>;
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};
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pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
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fsl,pins = <
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MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
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MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
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MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
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MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
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MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
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MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
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MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
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MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
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MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
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MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
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MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068
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>;
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};
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pinctrl_usdhc4_100mhz: usdhc4-100mhz {
|
|
fsl,pins = <
|
|
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
|
|
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
|
|
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
|
|
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
|
|
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
|
|
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
|
|
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
|
|
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
|
|
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
|
|
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc4_200mhz: usdhc4-200mhz {
|
|
fsl,pins = <
|
|
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
|
|
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
|
|
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
|
|
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
|
|
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
|
|
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
|
|
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
|
|
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
|
|
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
|
|
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
|
|
>;
|
|
};
|
|
};
|
|
|
|
&pcie {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcie>;
|
|
reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
|
|
reset-gpio-active-high;
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm1 {
|
|
#pwm-cells = <2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm2 {
|
|
#pwm-cells = <2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm6 {
|
|
#pwm-cells = <2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm6>;
|
|
status = "okay";
|
|
};
|
|
|
|
®_arm {
|
|
vin-supply = <&sw1a_reg>;
|
|
};
|
|
|
|
®_soc {
|
|
vin-supply = <&sw1a_reg>;
|
|
};
|
|
|
|
&snvs_poweroff {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg1 {
|
|
vbus-supply = <®_usb_otg1_vbus>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb_otg1_id>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg2 {
|
|
dr_mode = "host";
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
|
cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
|
|
keep-power-in-suspend;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc4 {
|
|
/* hs200-mode is currently unsupported because Vccq is on 3.1V, but
|
|
* not on necessary 1.8V.
|
|
*/
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
|
|
pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
|
|
bus-width = <8>;
|
|
keep-power-in-suspend;
|
|
non-removable;
|
|
cap-mmc-hw-reset;
|
|
status = "okay";
|
|
};
|