mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 19:10:13 +00:00
d0399a46e7
Synchronise device trees with linux-next next-20220708. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
535 lines
12 KiB
Text
535 lines
12 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2013 Sascha Hauer, Pengutronix
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*
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* Copyright 2013-2021 TQ-Systems GmbH
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* Author: Markus Niebel <Markus.Niebel@tq-group.com>
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*/
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/sound/fsl-imx-audmux.h>
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/ {
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aliases {
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mmc0 = &usdhc3;
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mmc1 = &usdhc2;
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/delete-property/ mmc2;
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/delete-property/ mmc3;
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rtc0 = &rtc0;
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};
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chosen {
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stdout-path = &uart2;
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};
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beeper: gpio-beeper {
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compatible = "gpio-beeper";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpiobeeper>;
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gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
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};
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gpio_buttons: gpio-buttons {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpiobuttons>;
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button1 {
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label = "s6";
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linux,code = <KEY_F6>;
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gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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button2 {
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label = "s7";
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linux,code = <KEY_F7>;
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gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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button3 {
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label = "s8";
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linux,code = <KEY_F8>;
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gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpioled>;
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led1 {
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label = "led1";
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gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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led2 {
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label = "led2";
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gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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reg_mba6_3p3v: regulator-mba6-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "supply-mba6-3p3v";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_pcie: regulator-pcie {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_regpcie>;
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regulator-name = "supply-pcie";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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/* PCIE.PWR_EN */
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gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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vin-supply = <®_mba6_3p3v>;
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};
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reg_vcc3v3_audio: regulator-vcc3v3-audio {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3-audio";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <®_mba6_3p3v>;
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};
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sound {
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compatible = "fsl,imx-audio-tlv320aic32x4";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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model = "imx-audio-tlv320aic32x4";
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ssi-controller = <&ssi1>;
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audio-codec = <&tlv320aic32x4>;
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audio-asrc = <&asrc>;
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audio-routing =
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"IN3_L", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"IN1_L", "Line In Jack",
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"IN1_R", "Line In Jack",
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"Line Out Jack", "LOL",
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"Line Out Jack", "LOR";
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mux-int-port = <1>;
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mux-ext-port = <3>;
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};
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};
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&audmux {
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status = "okay";
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ssi0 {
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fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
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fsl,port-config = <
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(IMX_AUDMUX_V2_PTCR_SYN |
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IMX_AUDMUX_V2_PTCR_TFSDIR |
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IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) |
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IMX_AUDMUX_V2_PTCR_TCLKDIR |
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IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3))
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IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)
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>;
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};
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aud3 {
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fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>;
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fsl,port-config = <
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IMX_AUDMUX_V2_PTCR_SYN
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IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
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>;
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can2>;
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status = "okay";
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
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cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
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};
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&fec {
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phy-mode = "rgmii-id";
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phy-handle = <ðphy>;
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mac-address = [00 00 00 00 00 00];
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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interrupt-parent = <&gpio1>;
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interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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reset-assert-us = <1000>;
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reset-deassert-us = <100000>;
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micrel,force-master;
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max-speed = <1000>;
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};
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};
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};
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&i2c1 {
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tlv320aic32x4: audio-codec@18 {
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compatible = "ti,tlv320aic32x4";
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reg = <0x18>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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clock-names = "mclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_codec>;
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ldoin-supply = <®_vcc3v3_audio>;
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iov-supply = <®_mba6_3p3v>;
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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status = "okay";
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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status = "okay";
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};
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&pwm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm4>;
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status = "okay";
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};
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&snvs_poweroff {
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status = "okay";
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};
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&ssi1 {
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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uart-has-rtscts;
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linux,rs485-enabled-at-boot-time;
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rs485-rts-active-low;
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rs485-rx-during-tx;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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uart-has-rtscts;
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status = "okay";
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};
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&usbh1 {
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disable-over-current;
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status = "okay";
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};
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&usbotg {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg>;
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power-active-high;
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over-current-active-low;
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srp-disable;
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hnp-disable;
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adp-disable;
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dr_mode = "otg";
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status = "okay";
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};
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/* SD card slot */
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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vmmc-supply = <®_mba6_3p3v>;
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bus-width = <4>;
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no-1-8-v;
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no-mmc;
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no-sdio;
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cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog1>;
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/* does not work on unmodified starter kit */
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/* fsl,ext-reset-output; */
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_audmux: audmuxgrp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
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MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
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MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
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MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
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>;
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};
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pinctrl_can1: can1grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099
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MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099
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>;
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};
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pinctrl_can2: can2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099
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MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099
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>;
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};
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pinctrl_codec: codecgrp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */
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>;
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};
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pinctrl_ecspi1_mba6: ecspimba6grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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/* FEC phy IRQ */
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MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
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/* FEC phy reset */
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
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/* DSE = 100, 100k up, SPEED = MED */
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
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/* DSE = 111, pull 100k up */
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
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/* DSE = 111, pull external */
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
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/* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
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>;
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};
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pinctrl_gpiobeeper: gpiobeepergrp {
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fsl,pins = <
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MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099
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>;
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};
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pinctrl_gpiobuttons: gpiobuttongrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099
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MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099
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MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099
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>;
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};
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pinctrl_gpioled: gpioledgrp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */
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MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
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MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
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MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
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MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
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MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
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MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
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MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
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MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
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MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
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MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
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MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
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MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
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MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
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MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
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MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
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MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
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MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
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MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
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MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
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MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
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MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
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MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
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MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
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MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
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MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
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>;
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};
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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/* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/
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MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
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MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
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MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
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>;
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};
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pinctrl_pwm1: pwm1grp {
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fsl,pins = <
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/* 100 k PD, DSE 120 OHM, SPPEED LO */
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MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
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>;
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};
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <
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/* 100 k PD, DSE 120 OHM, SPPEED LO */
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MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
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>;
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};
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pinctrl_pwm4: pwm4grp {
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fsl,pins = <
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/* 100 k PD, DSE 120 OHM, SPPEED LO */
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MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
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>;
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};
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pinctrl_regpcie: regpciegrp {
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fsl,pins = <
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/* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
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MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
|
|
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
|
|
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart4: uart4grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5: uart5grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
/* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
|
|
/* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
|
|
|
|
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
|
|
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
|
|
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
|
|
MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog1: wdog1grp {
|
|
fsl,pins = <
|
|
/* Watchdog out */
|
|
MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
|
|
>;
|
|
};
|
|
};
|