mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
0d331c035a
Add i.MX8QM MEK board support. Included a basic dts, enabled SPL FIT Boot log as below: U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) Normal Boot Trying to boot from MMC2_2 U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) CPU: NXP i.MX8QM RevB A53 at 142933 MHz Model: Freescale i.MX8QM MEK Board: iMX8QM MEK Build: SCFW 9330215b Boot: SD1 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: Error: ethernet@5b040000 address not set. eth-1: ethernet@5b040000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
184 lines
5 KiB
Text
184 lines
5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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*/
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/dts-v1/;
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#include "fsl-imx8qm.dtsi"
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#include "fsl-imx8qm-mek-u-boot.dtsi"
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/ {
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model = "Freescale i.MX8QM MEK";
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compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
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stdout-path = &lpuart0;
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};
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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off-on-delay = <4800>;
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enable-active-high;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx8qm-mek {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
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SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c
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SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
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SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
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SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
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SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
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SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
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SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
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SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
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SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
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SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
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SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
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SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
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SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
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SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_DMA_UART0_RX 0x06000020
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SC_P_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
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SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
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SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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};
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-txid";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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fsl,rgmii_rxc_dly;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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status = "disabled";
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};
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};
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};
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&lpuart0 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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