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https://github.com/AsahiLinux/u-boot
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6419f8e9fd
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
1. Each hart (in the middle of a function call) overwriting its own
stack and other harts' stacks.
(data-race and data-corruption)
2. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
69 lines
1.3 KiB
C
69 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*/
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#include <common.h>
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#include <asm/arch/eeprom.h>
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#include <asm/csr.h>
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#include <asm/sections.h>
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#include <dm.h>
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#include <linux/sizes.h>
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#include <log.h>
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#include <init.h>
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#define CSR_U74_FEATURE_DISABLE 0x7c1
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DECLARE_GLOBAL_DATA_PTR;
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static bool check_ddr_size(phys_size_t size)
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{
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switch (size) {
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case SZ_2:
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case SZ_4:
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case SZ_8:
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case SZ_16:
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return true;
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default:
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return false;
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}
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}
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int spl_soc_init(void)
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{
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int ret;
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struct udevice *dev;
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phys_size_t size;
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ret = fdtdec_setup_mem_size_base();
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if (ret)
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return ret;
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/* Read the definition of the DDR size from eeprom, and if not,
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* use the definition in DT
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*/
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size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
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if (check_ddr_size(size))
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gd->ram_size = size << 30;
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/* DDR init */
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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void harts_early_init(void)
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{
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/*
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* Feature Disable CSR
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*
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* Clear feature disable CSR to '0' to turn on all features for
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* each core. This operation must be in M-mode.
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*/
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if (CONFIG_IS_ENABLED(RISCV_MMODE))
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csr_write(CSR_U74_FEATURE_DISABLE, 0);
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}
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