u-boot/arch/arm/dts/sam9x60ek-u-boot.dtsi
Tudor Ambarus 228f9e0244 ARM: dts: at91: sam9x60ek: Enable qspi node
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.

Enable the qspi node together with the SST26VF064B qspi nor flash
memory. Booting from the QSPI NOR flash is now possible.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08 09:16:11 +03:00

132 lines
1.3 KiB
Text

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sam9x60-u-boot.dts - Device Tree file for SAM9X60 SoC.
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*/
/ {
chosen {
u-boot,dm-pre-reloc;
};
ahb {
u-boot,dm-pre-reloc;
apb {
u-boot,dm-pre-reloc;
pinctrl {
u-boot,dm-pre-reloc;
};
};
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
};
&dbgu {
u-boot,dm-pre-reloc;
};
&qspi {
u-boot,dm-pre-reloc;
};
&pinctrl_dbgu {
u-boot,dm-pre-reloc;
};
&pinctrl_sdhci0 {
u-boot,dm-pre-reloc;
};
&pinctrl_qspi {
u-boot,dm-pre-reloc;
};
&pioA {
u-boot,dm-pre-reloc;
};
&pioB {
u-boot,dm-pre-reloc;
};
&pmc {
u-boot,dm-pre-reloc;
};
&main {
u-boot,dm-pre-reloc;
};
&plla {
u-boot,dm-pre-reloc;
};
&mck {
u-boot,dm-pre-reloc;
};
&system {
u-boot,dm-pre-reloc;
};
&qspick {
u-boot,dm-pre-reloc;
};
&periph {
u-boot,dm-pre-reloc;
};
&pioA_clk {
u-boot,dm-pre-reloc;
};
&pioB_clk {
u-boot,dm-pre-reloc;
};
&sdhci0_clk {
u-boot,dm-pre-reloc;
};
&dbgu_clk {
u-boot,dm-pre-reloc;
};
&qspi_clk {
u-boot,dm-pre-reloc;
};
&generic {
u-boot,dm-pre-reloc;
};
&sdhci0_gclk {
u-boot,dm-pre-reloc;
};
&slowckc {
u-boot,dm-pre-reloc;
};
&slow_osc {
u-boot,dm-pre-reloc;
};
&slow_rc_osc {
u-boot,dm-pre-reloc;
};
&td_slck {
u-boot,dm-pre-reloc;
};
&md_slck {
u-boot,dm-pre-reloc;
};