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https://github.com/AsahiLinux/u-boot
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d02be21d30
The controller needs two clk, per clk and ipg clk, so let's add ipg clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
522 lines
12 KiB
C
522 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductors, Inc.
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <imx_lpi2c.h>
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#include <asm/arch/sys_proto.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#define LPI2C_FIFO_SIZE 4
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#define LPI2C_NACK_TOUT_MS 1
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#define LPI2C_TIMEOUT_MS 100
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static int bus_i2c_init(struct udevice *bus, int speed);
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/* Weak linked function for overridden by some SoC power function */
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int __weak init_i2c_power(unsigned i2c_num)
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{
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return 0;
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}
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static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
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{
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lpi2c_status_t result = LPI2C_SUCESS;
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u32 status;
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status = readl(®s->msr);
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if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
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result = LPI2C_BUSY;
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return result;
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}
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static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
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{
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lpi2c_status_t result = LPI2C_SUCESS;
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u32 val, status;
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status = readl(®s->msr);
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/* errors to check for */
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status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
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LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
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if (status) {
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if (status & LPI2C_MSR_PLTF_MASK)
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result = LPI2C_PIN_LOW_TIMEOUT_ERR;
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else if (status & LPI2C_MSR_ALF_MASK)
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result = LPI2C_ARB_LOST_ERR;
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else if (status & LPI2C_MSR_NDF_MASK)
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result = LPI2C_NAK_ERR;
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else if (status & LPI2C_MSR_FEF_MASK)
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result = LPI2C_FIFO_ERR;
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/* clear status flags */
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writel(0x7f00, ®s->msr);
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/* reset fifos */
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val = readl(®s->mcr);
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val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
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writel(val, ®s->mcr);
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}
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return result;
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}
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static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
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{
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lpi2c_status_t result = LPI2C_SUCESS;
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u32 txcount = 0;
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ulong start_time = get_timer(0);
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do {
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txcount = LPI2C_MFSR_TXCOUNT(readl(®s->mfsr));
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txcount = LPI2C_FIFO_SIZE - txcount;
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result = imx_lpci2c_check_clear_error(regs);
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if (result) {
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debug("i2c: wait for tx ready: result 0x%x\n", result);
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return result;
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}
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if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
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debug("i2c: wait for tx ready: timeout\n");
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return -1;
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}
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} while (!txcount);
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return result;
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}
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static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
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{
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struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
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lpi2c_status_t result = LPI2C_SUCESS;
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/* empty tx */
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if (!len)
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return result;
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while (len--) {
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result = bus_i2c_wait_for_tx_ready(regs);
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if (result) {
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debug("i2c: send wait for tx ready: %d\n", result);
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return result;
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}
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writel(*txbuf++, ®s->mtdr);
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}
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return result;
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}
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static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
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{
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struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
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lpi2c_status_t result = LPI2C_SUCESS;
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u32 val;
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ulong start_time = get_timer(0);
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/* empty read */
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if (!len)
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return result;
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result = bus_i2c_wait_for_tx_ready(regs);
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if (result) {
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debug("i2c: receive wait fot tx ready: %d\n", result);
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return result;
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}
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/* clear all status flags */
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writel(0x7f00, ®s->msr);
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/* send receive command */
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val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
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writel(val, ®s->mtdr);
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while (len--) {
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do {
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result = imx_lpci2c_check_clear_error(regs);
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if (result) {
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debug("i2c: receive check clear error: %d\n",
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result);
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return result;
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}
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if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
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debug("i2c: receive mrdr: timeout\n");
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return -1;
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}
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val = readl(®s->mrdr);
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} while (val & LPI2C_MRDR_RXEMPTY_MASK);
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*rxbuf++ = LPI2C_MRDR_DATA(val);
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}
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return result;
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}
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static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
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{
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lpi2c_status_t result;
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struct imx_lpi2c_reg *regs =
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(struct imx_lpi2c_reg *)devfdt_get_addr(bus);
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u32 val;
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result = imx_lpci2c_check_busy_bus(regs);
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if (result) {
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debug("i2c: start check busy bus: 0x%x\n", result);
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/* Try to init the lpi2c then check the bus busy again */
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bus_i2c_init(bus, 100000);
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result = imx_lpci2c_check_busy_bus(regs);
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if (result) {
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printf("i2c: Error check busy bus: 0x%x\n", result);
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return result;
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}
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}
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/* clear all status flags */
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writel(0x7f00, ®s->msr);
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/* turn off auto-stop condition */
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val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
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writel(val, ®s->mcfgr1);
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/* wait tx fifo ready */
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result = bus_i2c_wait_for_tx_ready(regs);
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if (result) {
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debug("i2c: start wait for tx ready: 0x%x\n", result);
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return result;
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}
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/* issue start command */
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val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
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writel(val, ®s->mtdr);
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return result;
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}
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static int bus_i2c_stop(struct udevice *bus)
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{
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lpi2c_status_t result;
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struct imx_lpi2c_reg *regs =
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(struct imx_lpi2c_reg *)devfdt_get_addr(bus);
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u32 status;
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ulong start_time;
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result = bus_i2c_wait_for_tx_ready(regs);
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if (result) {
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debug("i2c: stop wait for tx ready: 0x%x\n", result);
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return result;
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}
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/* send stop command */
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writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr);
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start_time = get_timer(0);
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while (1) {
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status = readl(®s->msr);
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result = imx_lpci2c_check_clear_error(regs);
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/* stop detect flag */
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if (status & LPI2C_MSR_SDF_MASK) {
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/* clear stop flag */
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status &= LPI2C_MSR_SDF_MASK;
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writel(status, ®s->msr);
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break;
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}
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if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
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debug("stop timeout\n");
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return -ETIMEDOUT;
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}
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}
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return result;
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}
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static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
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{
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lpi2c_status_t result;
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result = bus_i2c_start(bus, chip, 1);
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if (result)
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return result;
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result = bus_i2c_receive(bus, buf, len);
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if (result)
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return result;
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return result;
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}
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static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
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{
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lpi2c_status_t result;
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result = bus_i2c_start(bus, chip, 0);
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if (result)
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return result;
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result = bus_i2c_send(bus, buf, len);
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if (result)
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return result;
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return result;
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}
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u32 __weak imx_get_i2cclk(u32 i2c_num)
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{
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return 0;
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}
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static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
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{
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struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
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struct imx_lpi2c_reg *regs;
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u32 val;
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u32 preescale = 0, best_pre = 0, clkhi = 0;
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u32 best_clkhi = 0, abs_error = 0, rate;
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u32 error = 0xffffffff;
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u32 clock_rate;
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bool mode;
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int i;
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regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
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if (IS_ENABLED(CONFIG_CLK)) {
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clock_rate = clk_get_rate(&i2c_bus->per_clk);
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if (clock_rate <= 0) {
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dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
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return clock_rate;
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}
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} else {
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clock_rate = imx_get_i2cclk(bus->seq);
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if (!clock_rate)
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return -EPERM;
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}
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mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
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/* disable master mode */
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val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
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writel(val | LPI2C_MCR_MEN(0), ®s->mcr);
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for (preescale = 1; (preescale <= 128) &&
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(error != 0); preescale = 2 * preescale) {
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for (clkhi = 1; clkhi < 32; clkhi++) {
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if (clkhi == 1)
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rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
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else
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rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
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abs_error = speed > rate ? speed - rate : rate - speed;
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if (abs_error < error) {
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best_pre = preescale;
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best_clkhi = clkhi;
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error = abs_error;
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if (abs_error == 0)
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break;
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}
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}
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}
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/* Standard, fast, fast mode plus and ultra-fast transfers. */
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val = LPI2C_MCCR0_CLKHI(best_clkhi);
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if (best_clkhi < 2)
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val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
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else
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val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
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LPI2C_MCCR0_DATAVD(best_clkhi / 2);
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writel(val, ®s->mccr0);
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for (i = 0; i < 8; i++) {
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if (best_pre == (1 << i)) {
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best_pre = i;
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break;
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}
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}
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val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
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writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), ®s->mcfgr1);
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if (mode) {
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val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
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writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
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}
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return 0;
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}
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static int bus_i2c_init(struct udevice *bus, int speed)
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{
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struct imx_lpi2c_reg *regs;
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u32 val;
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int ret;
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regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
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/* reset peripheral */
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writel(LPI2C_MCR_RST_MASK, ®s->mcr);
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writel(0x0, ®s->mcr);
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/* Disable Dozen mode */
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writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr);
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/* host request disable, active high, external pin */
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val = readl(®s->mcfgr0);
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val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
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LPI2C_MCFGR0_HRSEL_MASK));
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val |= LPI2C_MCFGR0_HRPOL(0x1);
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writel(val, ®s->mcfgr0);
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/* pincfg and ignore ack */
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val = readl(®s->mcfgr1);
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val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
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val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
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val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
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writel(val, ®s->mcfgr1);
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ret = bus_i2c_set_bus_speed(bus, speed);
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/* enable lpi2c in master mode */
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val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
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writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
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debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
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return ret;
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}
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static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
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u32 chip_flags)
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{
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lpi2c_status_t result;
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result = bus_i2c_start(bus, chip, 0);
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if (result) {
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bus_i2c_stop(bus);
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bus_i2c_init(bus, 100000);
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return result;
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}
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result = bus_i2c_stop(bus);
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if (result)
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bus_i2c_init(bus, 100000);
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return result;
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}
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static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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{
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int ret = 0, ret_stop;
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for (; nmsgs > 0; nmsgs--, msg++) {
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
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if (msg->flags & I2C_M_RD)
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ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
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else {
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ret = bus_i2c_write(bus, msg->addr, msg->buf,
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msg->len);
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if (ret)
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break;
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}
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}
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if (ret)
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debug("i2c_write: error sending\n");
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ret_stop = bus_i2c_stop(bus);
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if (ret_stop)
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debug("i2c_xfer: stop bus error\n");
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ret |= ret_stop;
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return ret;
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}
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static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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return bus_i2c_set_bus_speed(bus, speed);
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}
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__weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
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{
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return 0;
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}
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static int imx_lpi2c_probe(struct udevice *bus)
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{
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struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
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fdt_addr_t addr;
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int ret;
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i2c_bus->driver_data = dev_get_driver_data(bus);
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addr = devfdt_get_addr(bus);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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i2c_bus->base = addr;
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i2c_bus->index = bus->seq;
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i2c_bus->bus = bus;
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/* power up i2c resource */
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ret = init_i2c_power(bus->seq);
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if (ret) {
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debug("init_i2c_power err = %d\n", ret);
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return ret;
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}
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if (IS_ENABLED(CONFIG_CLK)) {
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ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
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if (ret) {
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dev_err(bus, "Failed to get per clk\n");
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return ret;
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}
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ret = clk_enable(&i2c_bus->per_clk);
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if (ret) {
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dev_err(bus, "Failed to enable per clk\n");
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return ret;
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}
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ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
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if (ret) {
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dev_err(bus, "Failed to get ipg clk\n");
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return ret;
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}
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ret = clk_enable(&i2c_bus->ipg_clk);
|
|
if (ret) {
|
|
dev_err(bus, "Failed to enable ipg clk\n");
|
|
return ret;
|
|
}
|
|
} else {
|
|
/* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
|
|
ret = enable_i2c_clk(1, bus->seq);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
ret = bus_i2c_init(bus, 100000);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
debug("i2c : controller bus %d at 0x%lx , speed %d: ",
|
|
bus->seq, i2c_bus->base,
|
|
i2c_bus->speed);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_i2c_ops imx_lpi2c_ops = {
|
|
.xfer = imx_lpi2c_xfer,
|
|
.probe_chip = imx_lpi2c_probe_chip,
|
|
.set_bus_speed = imx_lpi2c_set_bus_speed,
|
|
};
|
|
|
|
static const struct udevice_id imx_lpi2c_ids[] = {
|
|
{ .compatible = "fsl,imx7ulp-lpi2c", },
|
|
{ .compatible = "fsl,imx8qm-lpi2c", },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(imx_lpi2c) = {
|
|
.name = "imx_lpi2c",
|
|
.id = UCLASS_I2C,
|
|
.of_match = imx_lpi2c_ids,
|
|
.probe = imx_lpi2c_probe,
|
|
.priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
|
|
.ops = &imx_lpi2c_ops,
|
|
};
|