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fe9efbca7b
Add clk controller driver for RK3308 SOC. This patch depends on Elaine's pll patch[0]. [0]http://patchwork.ozlabs.org/patch/1183718/ Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
387 lines
9.2 KiB
C
387 lines
9.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_VPLL0 3
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#define PLL_VPLL1 4
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#define ARMCLK 5
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/* sclk (special clocks) */
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#define USB480M 14
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#define SCLK_RTC32K 15
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#define SCLK_PVTM_CORE 16
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#define SCLK_UART0 17
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#define SCLK_UART1 18
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#define SCLK_UART2 19
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#define SCLK_UART3 20
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#define SCLK_UART4 21
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#define SCLK_I2C0 22
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#define SCLK_I2C1 23
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#define SCLK_I2C2 24
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#define SCLK_I2C3 25
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#define SCLK_PWM0 26
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#define SCLK_SPI0 27
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#define SCLK_SPI1 28
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#define SCLK_SPI2 29
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#define SCLK_TIMER0 30
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#define SCLK_TIMER1 31
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#define SCLK_TIMER2 32
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#define SCLK_TIMER3 33
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#define SCLK_TIMER4 34
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#define SCLK_TIMER5 35
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#define SCLK_TSADC 36
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#define SCLK_SARADC 37
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#define SCLK_OTP 38
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#define SCLK_OTP_USR 39
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#define SCLK_CPU_BOOST 40
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#define SCLK_CRYPTO 41
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#define SCLK_CRYPTO_APK 42
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#define SCLK_NANDC_DIV 43
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#define SCLK_NANDC_DIV50 44
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#define SCLK_NANDC 45
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#define SCLK_SDMMC_DIV 46
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#define SCLK_SDMMC_DIV50 47
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#define SCLK_SDMMC 48
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#define SCLK_SDMMC_DRV 49
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#define SCLK_SDMMC_SAMPLE 50
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#define SCLK_SDIO_DIV 51
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#define SCLK_SDIO_DIV50 52
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#define SCLK_SDIO 53
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#define SCLK_SDIO_DRV 54
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#define SCLK_SDIO_SAMPLE 55
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#define SCLK_EMMC_DIV 56
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#define SCLK_EMMC_DIV50 57
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#define SCLK_EMMC 58
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#define SCLK_EMMC_DRV 59
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#define SCLK_EMMC_SAMPLE 60
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#define SCLK_SFC 61
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#define SCLK_OTG_ADP 62
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#define SCLK_MAC_SRC 63
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#define SCLK_MAC 64
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#define SCLK_MAC_REF 65
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#define SCLK_MAC_RX_TX 66
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#define SCLK_MAC_RMII 67
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#define SCLK_DDR_MON_TIMER 68
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#define SCLK_DDR_MON 69
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#define SCLK_DDRCLK 70
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#define SCLK_PMU 71
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#define SCLK_USBPHY_REF 72
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#define SCLK_WIFI 73
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#define SCLK_PVTM_PMU 74
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#define SCLK_PDM 75
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#define SCLK_I2S0_8CH_TX 76
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#define SCLK_I2S0_8CH_TX_OUT 77
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#define SCLK_I2S0_8CH_RX 78
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#define SCLK_I2S0_8CH_RX_OUT 79
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#define SCLK_I2S1_8CH_TX 80
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#define SCLK_I2S1_8CH_TX_OUT 81
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#define SCLK_I2S1_8CH_RX 82
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#define SCLK_I2S1_8CH_RX_OUT 83
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#define SCLK_I2S2_8CH_TX 84
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#define SCLK_I2S2_8CH_TX_OUT 85
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#define SCLK_I2S2_8CH_RX 86
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#define SCLK_I2S2_8CH_RX_OUT 87
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#define SCLK_I2S3_8CH_TX 88
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#define SCLK_I2S3_8CH_TX_OUT 89
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#define SCLK_I2S3_8CH_RX 90
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#define SCLK_I2S3_8CH_RX_OUT 91
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#define SCLK_I2S0_2CH 92
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#define SCLK_I2S0_2CH_OUT 93
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#define SCLK_I2S1_2CH 94
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#define SCLK_I2S1_2CH_OUT 95
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#define SCLK_SPDIF_TX_DIV 96
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#define SCLK_SPDIF_TX_DIV50 97
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#define SCLK_SPDIF_TX 98
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#define SCLK_SPDIF_RX_DIV 99
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#define SCLK_SPDIF_RX_DIV50 100
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#define SCLK_SPDIF_RX 101
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#define SCLK_I2S0_8CH_TX_MUX 102
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#define SCLK_I2S0_8CH_RX_MUX 103
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#define SCLK_I2S1_8CH_TX_MUX 104
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#define SCLK_I2S1_8CH_RX_MUX 105
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#define SCLK_I2S2_8CH_TX_MUX 106
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#define SCLK_I2S2_8CH_RX_MUX 107
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#define SCLK_I2S3_8CH_TX_MUX 108
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#define SCLK_I2S3_8CH_RX_MUX 109
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#define SCLK_I2S0_8CH_TX_SRC 110
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#define SCLK_I2S0_8CH_RX_SRC 111
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#define SCLK_I2S1_8CH_TX_SRC 112
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#define SCLK_I2S1_8CH_RX_SRC 113
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#define SCLK_I2S2_8CH_TX_SRC 114
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#define SCLK_I2S2_8CH_RX_SRC 115
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#define SCLK_I2S3_8CH_TX_SRC 116
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#define SCLK_I2S3_8CH_RX_SRC 117
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#define SCLK_I2S0_2CH_SRC 118
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#define SCLK_I2S1_2CH_SRC 119
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#define SCLK_PWM1 120
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#define SCLK_PWM2 121
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#define SCLK_OWIRE 122
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/* dclk */
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#define DCLK_VOP 125
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/* aclk */
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#define ACLK_BUS_SRC 130
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#define ACLK_BUS 131
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#define ACLK_PERI_SRC 132
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#define ACLK_PERI 133
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#define ACLK_MAC 134
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#define ACLK_CRYPTO 135
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#define ACLK_VOP 136
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#define ACLK_GIC 137
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#define ACLK_DMAC0 138
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#define ACLK_DMAC1 139
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/* hclk */
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#define HCLK_BUS 150
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#define HCLK_PERI 151
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#define HCLK_AUDIO 152
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#define HCLK_NANDC 153
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#define HCLK_SDMMC 154
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#define HCLK_SDIO 155
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#define HCLK_EMMC 156
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#define HCLK_SFC 157
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#define HCLK_OTG 158
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#define HCLK_HOST 159
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#define HCLK_HOST_ARB 160
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#define HCLK_PDM 161
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#define HCLK_SPDIFTX 162
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#define HCLK_SPDIFRX 163
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#define HCLK_I2S0_8CH 164
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#define HCLK_I2S1_8CH 165
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#define HCLK_I2S2_8CH 166
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#define HCLK_I2S3_8CH 167
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#define HCLK_I2S0_2CH 168
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#define HCLK_I2S1_2CH 169
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#define HCLK_VAD 170
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#define HCLK_CRYPTO 171
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#define HCLK_VOP 172
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/* pclk */
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#define PCLK_BUS 190
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#define PCLK_DDR 191
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#define PCLK_PERI 192
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#define PCLK_PMU 193
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#define PCLK_AUDIO 194
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#define PCLK_MAC 195
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#define PCLK_ACODEC 196
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#define PCLK_UART0 197
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#define PCLK_UART1 198
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#define PCLK_UART2 199
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#define PCLK_UART3 200
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#define PCLK_UART4 201
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#define PCLK_I2C0 202
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#define PCLK_I2C1 203
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#define PCLK_I2C2 204
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#define PCLK_I2C3 205
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#define PCLK_PWM0 206
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#define PCLK_SPI0 207
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#define PCLK_SPI1 208
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#define PCLK_SPI2 209
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#define PCLK_SARADC 210
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#define PCLK_TSADC 211
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#define PCLK_TIMER 212
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#define PCLK_OTP_NS 213
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#define PCLK_WDT 214
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#define PCLK_GPIO0 215
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#define PCLK_GPIO1 216
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#define PCLK_GPIO2 217
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#define PCLK_GPIO3 218
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#define PCLK_GPIO4 219
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#define PCLK_SGRF 220
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#define PCLK_GRF 221
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#define PCLK_USBSD_DET 222
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#define PCLK_DDR_UPCTL 223
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#define PCLK_DDR_MON 224
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#define PCLK_DDRPHY 225
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#define PCLK_DDR_STDBY 226
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#define PCLK_USB_GRF 227
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#define PCLK_CRU 228
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#define PCLK_OTP_PHY 229
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#define PCLK_CPU_BOOST 230
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#define PCLK_PWM1 231
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#define PCLK_PWM2 232
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#define PCLK_CAN 233
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#define PCLK_OWIRE 234
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#define CLK_NR_CLKS (PCLK_OWIRE + 1)
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/* soft-reset indices */
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/* cru_softrst_con0 */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE2_PO 2
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#define SRST_CORE3_PO 3
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#define SRST_CORE0 4
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#define SRST_CORE1 5
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#define SRST_CORE2 6
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#define SRST_CORE3 7
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#define SRST_CORE0_DBG 8
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#define SRST_CORE1_DBG 9
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#define SRST_CORE2_DBG 10
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#define SRST_CORE3_DBG 11
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#define SRST_TOPDBG 12
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#define SRST_CORE_NOC 13
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#define SRST_STRC_A 14
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#define SRST_L2C 15
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/* cru_softrst_con1 */
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#define SRST_DAP 16
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#define SRST_CORE_PVTM 17
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#define SRST_CORE_PRF 18
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#define SRST_CORE_GRF 19
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#define SRST_DDRUPCTL 20
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#define SRST_DDRUPCTL_P 22
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#define SRST_MSCH 23
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#define SRST_DDRMON_P 25
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#define SRST_DDRSTDBY_P 26
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#define SRST_DDRSTDBY 27
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#define SRST_DDRPHY 28
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#define SRST_DDRPHY_DIV 29
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#define SRST_DDRPHY_P 30
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/* cru_softrst_con2 */
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#define SRST_BUS_NIU_H 32
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#define SRST_USB_NIU_P 33
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#define SRST_CRYPTO_A 34
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#define SRST_CRYPTO_H 35
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#define SRST_CRYPTO 36
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#define SRST_CRYPTO_APK 37
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#define SRST_VOP_A 38
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#define SRST_VOP_H 39
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#define SRST_VOP_D 40
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#define SRST_INTMEM_A 41
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#define SRST_ROM_H 42
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#define SRST_GIC_A 43
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#define SRST_UART0_P 44
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#define SRST_UART0 45
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#define SRST_UART1_P 46
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#define SRST_UART1 47
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/* cru_softrst_con3 */
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#define SRST_UART2_P 48
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#define SRST_UART2 49
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#define SRST_UART3_P 50
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#define SRST_UART3 51
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#define SRST_UART4_P 52
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#define SRST_UART4 53
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#define SRST_I2C0_P 54
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#define SRST_I2C0 55
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#define SRST_I2C1_P 56
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#define SRST_I2C1 57
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#define SRST_I2C2_P 58
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#define SRST_I2C2 59
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#define SRST_I2C3_P 60
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#define SRST_I2C3 61
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#define SRST_PWM0_P 62
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#define SRST_PWM0 63
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/* cru_softrst_con4 */
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#define SRST_SPI0_P 64
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#define SRST_SPI0 65
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#define SRST_SPI1_P 66
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#define SRST_SPI1 67
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#define SRST_SPI2_P 68
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#define SRST_SPI2 69
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#define SRST_SARADC_P 70
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#define SRST_TSADC_P 71
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#define SRST_TSADC 72
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#define SRST_TIMER0_P 73
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#define SRST_TIMER0 74
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#define SRST_TIMER1 75
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#define SRST_TIMER2 76
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#define SRST_TIMER3 77
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#define SRST_TIMER4 78
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#define SRST_TIMER5 79
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/* cru_softrst_con5 */
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#define SRST_OTP_NS_P 80
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#define SRST_OTP_NS_SBPI 81
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#define SRST_OTP_NS_USR 82
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#define SRST_OTP_PHY_P 83
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#define SRST_OTP_PHY 84
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#define SRST_GPIO0_P 86
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#define SRST_GPIO1_P 87
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#define SRST_GPIO2_P 88
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#define SRST_GPIO3_P 89
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#define SRST_GPIO4_P 90
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#define SRST_GRF_P 91
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#define SRST_USBSD_DET_P 92
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#define SRST_PMU 93
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#define SRST_PMU_PVTM 94
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#define SRST_USB_GRF_P 95
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/* cru_softrst_con6 */
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#define SRST_CPU_BOOST 96
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#define SRST_CPU_BOOST_P 97
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#define SRST_PWM1_P 98
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#define SRST_PWM1 99
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#define SRST_PWM2_P 100
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#define SRST_PWM2 101
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#define SRST_PERI_NIU_A 104
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#define SRST_PERI_NIU_H 105
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#define SRST_PERI_NIU_p 106
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#define SRST_USB2OTG_H 107
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#define SRST_USB2OTG 108
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#define SRST_USB2OTG_ADP 109
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#define SRST_USB2HOST_H 110
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#define SRST_USB2HOST_ARB_H 111
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/* cru_softrst_con7 */
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#define SRST_USB2HOST_AUX_H 112
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#define SRST_USB2HOST_EHCI 113
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#define SRST_USB2HOST 114
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#define SRST_USBPHYPOR 115
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#define SRST_UTMI0 116
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#define SRST_UTMI1 117
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#define SRST_SDIO_H 118
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#define SRST_EMMC_H 119
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#define SRST_SFC_H 120
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#define SRST_SFC 121
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#define SRST_SD_H 122
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#define SRST_NANDC_H 123
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#define SRST_NANDC_N 124
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#define SRST_MAC_A 125
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#define SRST_CAN_P 126
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#define SRST_OWIRE_P 127
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/* cru_softrst_con8 */
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#define SRST_AUDIO_NIU_H 128
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#define SRST_AUDIO_NIU_P 129
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#define SRST_PDM_H 130
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#define SRST_PDM_M 131
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#define SRST_SPDIFTX_H 132
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#define SRST_SPDIFTX_M 133
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#define SRST_SPDIFRX_H 134
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#define SRST_SPDIFRX_M 135
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#define SRST_I2S0_8CH_H 136
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#define SRST_I2S0_8CH_TX_M 137
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#define SRST_I2S0_8CH_RX_M 138
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#define SRST_I2S1_8CH_H 139
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#define SRST_I2S1_8CH_TX_M 140
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#define SRST_I2S1_8CH_RX_M 141
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#define SRST_I2S2_8CH_H 142
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#define SRST_I2S2_8CH_TX_M 143
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/* cru_softrst_con9 */
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#define SRST_I2S2_8CH_RX_M 144
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#define SRST_I2S3_8CH_H 145
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#define SRST_I2S3_8CH_TX_M 146
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#define SRST_I2S3_8CH_RX_M 147
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#define SRST_I2S0_2CH_H 148
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#define SRST_I2S0_2CH_M 149
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#define SRST_I2S1_2CH_H 150
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#define SRST_I2S1_2CH_M 151
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#define SRST_VAD_H 152
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#define SRST_ACODEC_P 153
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#endif
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