mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
a94a4071d4
Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
185 lines
6.1 KiB
C
185 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef K3_NAVSS_UDMA_HWDEF_H_
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#define K3_NAVSS_UDMA_HWDEF_H_
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#include <linux/bitops.h>
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#define UDMA_PSIL_DST_THREAD_ID_OFFSET 0x8000
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/* Global registers */
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#define UDMA_REV_REG 0x0
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#define UDMA_PERF_CTL_REG 0x4
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#define UDMA_EMU_CTL_REG 0x8
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#define UDMA_PSIL_TO_REG 0x10
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#define UDMA_UTC_CTL_REG 0x1c
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#define UDMA_CAP_REG(i) (0x20 + (i * 4))
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#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
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#define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
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/* RX Flow regs */
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#define UDMA_RFLOW_RFA_REG 0x0
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#define UDMA_RFLOW_RFB_REG 0x4
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#define UDMA_RFLOW_RFC_REG 0x8
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#define UDMA_RFLOW_RFD_REG 0xc
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#define UDMA_RFLOW_RFE_REG 0x10
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#define UDMA_RFLOW_RFF_REG 0x14
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#define UDMA_RFLOW_RFG_REG 0x18
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#define UDMA_RFLOW_RFH_REG 0x1c
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#define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG)
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/* TX chan regs */
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#define UDMA_TCHAN_TCFG_REG 0x0
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#define UDMA_TCHAN_TCREDIT_REG 0x4
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#define UDMA_TCHAN_TCQ_REG 0x14
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#define UDMA_TCHAN_TOES_REG(i) (0x20 + (i) * 4)
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#define UDMA_TCHAN_TEOES_REG 0x60
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#define UDMA_TCHAN_TPRI_CTRL_REG 0x64
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#define UDMA_TCHAN_THREAD_ID_REG 0x68
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#define UDMA_TCHAN_TFIFO_DEPTH_REG 0x70
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#define UDMA_TCHAN_TST_SCHED_REG 0x80
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/* RX chan regs */
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#define UDMA_RCHAN_RCFG_REG 0x0
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#define UDMA_RCHAN_RCQ_REG 0x14
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#define UDMA_RCHAN_ROES_REG(i) (0x20 + (i) * 4)
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#define UDMA_RCHAN_REOES_REG 0x60
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#define UDMA_RCHAN_RPRI_CTRL_REG 0x64
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#define UDMA_RCHAN_THREAD_ID_REG 0x68
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#define UDMA_RCHAN_RST_SCHED_REG 0x80
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#define UDMA_RCHAN_RFLOW_RNG_REG 0xf0
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/* TX chan RT regs */
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#define UDMA_TCHAN_RT_CTL_REG 0x0
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#define UDMA_TCHAN_RT_SWTRIG_REG 0x8
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#define UDMA_TCHAN_RT_STDATA_REG 0x80
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#define UDMA_TCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4))
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#define UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG \
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UDMA_TCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */
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#define UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG \
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UDMA_TCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */
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#define UDMA_TCHAN_RT_PEER_BCNT_REG \
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UDMA_TCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */
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#define UDMA_TCHAN_RT_PEER_RT_EN_REG \
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UDMA_TCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */
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#define UDMA_TCHAN_RT_PCNT_REG 0x400
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#define UDMA_TCHAN_RT_BCNT_REG 0x408
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#define UDMA_TCHAN_RT_SBCNT_REG 0x410
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/* RX chan RT regs */
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#define UDMA_RCHAN_RT_CTL_REG 0x0
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#define UDMA_RCHAN_RT_SWTRIG_REG 0x8
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#define UDMA_RCHAN_RT_STDATA_REG 0x80
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#define UDMA_RCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4))
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#define UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG \
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UDMA_RCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */
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#define UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG \
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UDMA_RCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */
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#define UDMA_RCHAN_RT_PEER_BCNT_REG \
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UDMA_RCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */
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#define UDMA_RCHAN_RT_PEER_RT_EN_REG \
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UDMA_RCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */
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#define UDMA_RCHAN_RT_PCNT_REG 0x400
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#define UDMA_RCHAN_RT_BCNT_REG 0x408
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#define UDMA_RCHAN_RT_SBCNT_REG 0x410
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/* UDMA_TCHAN_TCFG_REG/UDMA_RCHAN_RCFG_REG */
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#define UDMA_CHAN_CFG_PAUSE_ON_ERR BIT(31)
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#define UDMA_TCHAN_CFG_FILT_EINFO BIT(30)
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#define UDMA_TCHAN_CFG_FILT_PSWORDS BIT(29)
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#define UDMA_CHAN_CFG_ATYPE_MASK GENMASK(25, 24)
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#define UDMA_CHAN_CFG_ATYPE_SHIFT 24
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#define UDMA_CHAN_CFG_CHAN_TYPE_MASK GENMASK(19, 16)
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#define UDMA_CHAN_CFG_CHAN_TYPE_SHIFT 16
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/*
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* PBVR - using pass by value rings
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* PBRR - using pass by reference rings
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* 3RDP - Third Party DMA
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* BC - Block Copy
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* SB - single buffer packet mode enabled
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*/
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#define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR \
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(2 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_SB_PBRR \
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(3 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBRR \
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(10 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBVR \
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(11 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR \
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(12 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_RCHAN_CFG_IGNORE_SHORT BIT(15)
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#define UDMA_RCHAN_CFG_IGNORE_LONG BIT(14)
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#define UDMA_TCHAN_CFG_SUPR_TDPKT BIT(8)
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#define UDMA_CHAN_CFG_FETCH_SIZE_MASK GENMASK(6, 0)
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#define UDMA_CHAN_CFG_FETCH_SIZE_SHIFT 0
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/* UDMA_TCHAN_RT_CTL_REG/UDMA_RCHAN_RT_CTL_REG */
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#define UDMA_CHAN_RT_CTL_EN BIT(31)
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#define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
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#define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
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#define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
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#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
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/* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */
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#define UDMA_PEER_RT_EN_ENABLE BIT(31)
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#define UDMA_PEER_RT_EN_TEARDOWN BIT(30)
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#define UDMA_PEER_RT_EN_PAUSE BIT(29)
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#define UDMA_PEER_RT_EN_FLUSH BIT(28)
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#define UDMA_PEER_RT_EN_IDLE BIT(1)
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/* RX Flow reg RFA */
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#define UDMA_RFLOW_RFA_EINFO BIT(30)
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#define UDMA_RFLOW_RFA_PSINFO BIT(29)
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#define UDMA_RFLOW_RFA_ERR_HANDLING BIT(28)
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#define UDMA_RFLOW_RFA_DESC_TYPE_MASK GENMASK(27, 26)
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#define UDMA_RFLOW_RFA_DESC_TYPE_SHIFT 26
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#define UDMA_RFLOW_RFA_PS_LOC BIT(25)
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#define UDMA_RFLOW_RFA_SOP_OFF_MASK GENMASK(24, 16)
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#define UDMA_RFLOW_RFA_SOP_OFF_SHIFT 16
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#define UDMA_RFLOW_RFA_DEST_QNUM_MASK GENMASK(15, 0)
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#define UDMA_RFLOW_RFA_DEST_QNUM_SHIFT 0
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/* RX Flow reg RFC */
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#define UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT 28
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#define UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT 24
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#define UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT 20
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#define UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT 16
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/*
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* UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG /
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* UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG
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*/
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#define PDMA_STATIC_TR_X_MASK GENMASK(26, 24)
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#define PDMA_STATIC_TR_X_SHIFT (24)
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#define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0)
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#define PDMA_STATIC_TR_Y_SHIFT (0)
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#define PDMA_STATIC_TR_Y(x) \
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(((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK)
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#define PDMA_STATIC_TR_X(x) \
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(((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK)
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/*
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* UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG /
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* UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG
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*/
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#define PDMA_STATIC_TR_Z_MASK GENMASK(11, 0)
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#define PDMA_STATIC_TR_Z_SHIFT (0)
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#define PDMA_STATIC_TR_Z(x) \
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(((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK)
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#endif /* K3_NAVSS_UDMA_HWDEF_H_ */
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