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6c869637fe
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
245 lines
9.5 KiB
Text
245 lines
9.5 KiB
Text
NAND FLASH commands and notes
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See NOTE below!!!
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# (C) Copyright 2003
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# Dave Ellis, SIXNET, dge@sixnetio.com
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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Commands:
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nand bad
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Print a list of all of the bad blocks in the current device.
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nand device
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Print information about the current NAND device.
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nand device num
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Make device `num' the current device and print information about it.
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nand erase off|partition size
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nand erase clean [off|partition size]
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Erase `size' bytes starting at offset `off'. Alternatively partition
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name can be specified, in this case size will be eventually limited
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to not exceed partition size (this behaviour applies also to read
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and write commands). Only complete erase blocks can be erased.
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If `erase' is specified without an offset or size, the entire flash
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is erased. If `erase' is specified with partition but without an
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size, the entire partition is erased.
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If `clean' is specified, a JFFS2-style clean marker is written to
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each block after it is erased.
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This command will not erase blocks that are marked bad. There is
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a debug option in cmd_nand.c to allow bad blocks to be erased.
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Please read the warning there before using it, as blocks marked
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bad by the manufacturer must _NEVER_ be erased.
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nand info
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Print information about all of the NAND devices found.
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nand read addr ofs|partition size
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Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
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are marked bad are skipped. If a page cannot be read because an
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uncorrectable data error is found, the command stops with an error.
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nand read.oob addr ofs|partition size
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Read `size' bytes from the out-of-band data area corresponding to
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`ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
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data for one 512-byte page or 2 256-byte pages. There is no check
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for bad blocks or ECC errors.
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nand write addr ofs|partition size
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Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
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are marked bad are skipped. If a page cannot be read because an
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uncorrectable data error is found, the command stops with an error.
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As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
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as long as the image is short enough to fit even after skipping the
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bad blocks. Compact images, such as those produced by mkfs.jffs2
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should work well, but loading an image copied from another flash is
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going to be trouble if there are any bad blocks.
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nand write.oob addr ofs|partition size
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Write `size' bytes from `addr' to the out-of-band data area
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corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
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of data for one 512-byte page or 2 256-byte pages. There is no check
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for bad blocks.
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Configuration Options:
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CONFIG_CMD_NAND
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Enables NAND support and commmands.
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CONFIG_MTD_NAND_ECC_JFFS2
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Define this if you want the Error Correction Code information in
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the out-of-band data to be formatted to match the JFFS2 file system.
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CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for
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someone to implement.
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CONFIG_SYS_MAX_NAND_DEVICE
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The maximum number of NAND devices you want to support.
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NAND Interface:
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#define NAND_WAIT_READY(nand)
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Wait until the NAND flash is ready. Typically this would be a
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loop waiting for the READY/BUSY line from the flash to indicate it
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it is ready.
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#define WRITE_NAND_COMMAND(d, adr)
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Write the command byte `d' to the flash at `adr' with the
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CLE (command latch enable) line true. If your board uses writes to
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different addresses to control CLE and ALE, you can modify `adr'
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to be the appropriate address here. If your board uses I/O registers
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to control them, it is probably better to let NAND_CTL_SETCLE()
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and company do it.
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#define WRITE_NAND_ADDRESS(d, adr)
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Write the address byte `d' to the flash at `adr' with the
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ALE (address latch enable) line true. If your board uses writes to
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different addresses to control CLE and ALE, you can modify `adr'
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to be the appropriate address here. If your board uses I/O registers
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to control them, it is probably better to let NAND_CTL_SETALE()
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and company do it.
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#define WRITE_NAND(d, adr)
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Write the data byte `d' to the flash at `adr' with the
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ALE and CLE lines false. If your board uses writes to
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different addresses to control CLE and ALE, you can modify `adr'
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to be the appropriate address here. If your board uses I/O registers
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to control them, it is probably better to let NAND_CTL_CLRALE()
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and company do it.
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#define READ_NAND(adr)
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Read a data byte from the flash at `adr' with the
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ALE and CLE lines false. If your board uses reads from
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different addresses to control CLE and ALE, you can modify `adr'
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to be the appropriate address here. If your board uses I/O registers
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to control them, it is probably better to let NAND_CTL_CLRALE()
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and company do it.
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#define NAND_DISABLE_CE(nand)
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Set CE (Chip Enable) low to enable the NAND flash.
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#define NAND_ENABLE_CE(nand)
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Set CE (Chip Enable) high to disable the NAND flash.
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#define NAND_CTL_CLRALE(nandptr)
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Set ALE (address latch enable) low. If ALE control is handled by
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WRITE_NAND_ADDRESS() this can be empty.
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#define NAND_CTL_SETALE(nandptr)
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Set ALE (address latch enable) high. If ALE control is handled by
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WRITE_NAND_ADDRESS() this can be empty.
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#define NAND_CTL_CLRCLE(nandptr)
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Set CLE (command latch enable) low. If CLE control is handled by
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WRITE_NAND_ADDRESS() this can be empty.
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#define NAND_CTL_SETCLE(nandptr)
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Set CLE (command latch enable) high. If CLE control is handled by
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WRITE_NAND_ADDRESS() this can be empty.
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More Definitions:
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These definitions are needed in the board configuration for now, but
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may really belong in a header file.
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TODO: Figure which ones are truly configuration settings and rename
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them to CONFIG_SYS_NAND_... and move the rest somewhere appropriate.
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_SYS_DAVINCI_BROKEN_ECC
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Versions of U-Boot <= 1.3.3 and Montavista Linux kernels
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generated bogus ECCs on large-page NAND. Both large and small page
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NAND ECCs were incompatible with the Linux davinci git tree (since
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NAND was integrated in 2.6.24).
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Turn this ON if you want backwards compatibility.
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Turn this OFF if you want U-Boot and the Linux davinci git kernel
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to use the same ECC format.
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NOTE:
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=====
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We now use a complete rewrite of the NAND code based on what is in
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2.6.12 Linux kernel.
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The old NAND handling code has been re-factored and is now confined
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to only board-specific files and - unfortunately - to the DoC code
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(see below). A new configuration variable has been introduced:
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CONFIG_NAND_LEGACY, which has to be defined in the board config file if
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that board uses legacy code.
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The necessary changes have been made to all affected boards, and no
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build breakage has been introduced, except for NETTA and NETTA_ISDN
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targets from MAKEALL. This is due to the fact that these two boards
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use JFFS, which has been adopted to use the new NAND, and at the same
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time use NAND in legacy mode. The breakage will disappear when the
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board-specific code is changed to the new NAND.
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As mentioned above, the legacy code is still used by the DoC subsystem.
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The consequence of this is that the legacy NAND can't be removed from
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the tree until the DoC is ported to use the new NAND support (or boards
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with DoC will break).
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Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
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JFFS2 related commands:
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implement "nand erase clean" and old "nand erase"
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using both the new code which is able to skip bad blocks
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"nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
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Miscellaneous and testing commands:
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"markbad [offset]"
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create an artificial bad block (for testing bad block handling)
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"scrub [offset length]"
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like "erase" but don't skip bad block. Instead erase them.
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DANGEROUS!!! Factory set bad blocks will be lost. Use only
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to remove artificial bad blocks created with the "markbad" command.
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NAND locking command (for chips with active LOCKPRE pin)
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"nand lock"
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set NAND chip to lock state (all pages locked)
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"nand lock tight"
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set NAND chip to lock tight state (software can't change locking anymore)
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"nand lock status"
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displays current locking status of all pages
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"nand unlock [offset] [size]"
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unlock consecutive area (can be called multiple times for different areas)
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I have tested the code with board containing 128MiB NAND large page chips
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and 32MiB small page chips.
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