mirror of
https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
195 lines
4.4 KiB
C
195 lines
4.4 KiB
C
/*
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* Board functions for IGEP COM AQUILA/CYGNUS based boards
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*
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* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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/* MII mode defines */
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#define RMII_MODE_ENABLE 0x4D
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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#ifdef CONFIG_SPL_BUILD
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
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.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
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.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
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.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = K4B2G1646EBIH9_RATIO,
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.cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
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.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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.cmd1csratio = K4B2G1646EBIH9_RATIO,
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.cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
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.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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.cmd2csratio = K4B2G1646EBIH9_RATIO,
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.cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
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.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
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.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
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.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
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.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
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.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
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.zq_config = K4B2G1646EBIH9_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
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};
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#endif
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/*
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* Early system init of muxing and clocks.
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*/
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void s_init(void)
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{
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/*
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* Save the boot parameters passed from romcode.
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* We cannot delay the saving further than this,
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* to prevent overwrites.
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*/
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#ifdef CONFIG_SPL_BUILD
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save_omap_boot_params();
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#endif
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(0xAAAA, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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#ifdef CONFIG_SPL_BUILD
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init();
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/* Enable RTC32K clock */
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rtc32k_enable();
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enable_uart0_pin_mux();
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uart_soft_reset();
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gd = &gdata;
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preloader_console_init();
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/* Configure board pin mux */
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enable_board_pin_mux();
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config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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#endif
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}
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
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gpmc_init();
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return 0;
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}
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#if defined(CONFIG_DRIVER_TI_CPSW)
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_id = 0,
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.phy_if = PHY_INTERFACE_MODE_RMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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int rv, ret = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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writel(RMII_MODE_ENABLE, &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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ret += rv;
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return ret;
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}
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#endif
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