mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 13:14:27 +00:00
77ecf95f22
Add Falcon mode support, which allows the SPL to load and jump to the Linux kernel directly, without the need of loading U-Boot proper. CONFIG_SPL_OS_BOOT=y needs to be passed in the defconfig in order to use Falcon mode. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
314 lines
8.4 KiB
C
314 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Technexion Ltd.
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*
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* Author: Richard Hu <richard.hu@technexion.com>
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* Fabio Estevam <festevam@gmail.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <spl.h>
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#if defined(CONFIG_SPL_BUILD)
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#include <asm/arch/mx6-ddr.h>
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#define IMX6DQ_DRIVE_STRENGTH 0x30
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#define IMX6SDL_DRIVE_STRENGTH 0x28
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* Break into full U-Boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif
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/* configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_cas = IMX6DQ_DRIVE_STRENGTH,
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.dram_ras = IMX6DQ_DRIVE_STRENGTH,
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.dram_reset = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_cas = IMX6SDL_DRIVE_STRENGTH,
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.dram_ras = IMX6SDL_DRIVE_STRENGTH,
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.dram_reset = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
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};
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6SDL_DRIVE_STRENGTH,
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.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
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};
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/* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
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static struct mx6_ddr3_cfg h5t04g63afr = {
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.mem_speed = 800,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1500,
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.trcmin = 5250,
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.trasmin = 3750,
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};
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/* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
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static struct mx6_ddr3_cfg h5tq2g63ffr = {
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.mem_speed = 800,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1500,
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.trcmin = 5250,
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.trasmin = 3750,
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};
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static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
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.p0_mpwldectrl0 = 0x00000000,
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.p0_mpwldectrl1 = 0x00000000,
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.p1_mpwldectrl0 = 0x00000000,
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.p1_mpwldectrl1 = 0x00000000,
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.p0_mpdgctrl0 = 0x032C0340,
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.p0_mpdgctrl1 = 0x03300324,
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.p1_mpdgctrl0 = 0x032C0338,
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.p1_mpdgctrl1 = 0x03300274,
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.p0_mprddlctl = 0x423A383E,
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.p1_mprddlctl = 0x3638323E,
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.p0_mpwrdlctl = 0x363C4640,
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.p1_mpwrdlctl = 0x4034423C,
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};
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/* DDR 32bit */
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static struct mx6_ddr_sysinfo mem_s = {
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.dsize = 1,
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.cs1_mirror = 0,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 0,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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};
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static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
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.p0_mpwldectrl0 = 0x001f001f,
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.p0_mpwldectrl1 = 0x001f001f,
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.p1_mpwldectrl0 = 0x001f001f,
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.p1_mpwldectrl1 = 0x001f001f,
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.p0_mpdgctrl0 = 0x420e020e,
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.p0_mpdgctrl1 = 0x02000200,
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.p1_mpdgctrl0 = 0x42020202,
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.p1_mpdgctrl1 = 0x01720172,
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.p0_mprddlctl = 0x494c4f4c,
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.p1_mprddlctl = 0x4a4c4c49,
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.p0_mpwrdlctl = 0x3f3f3133,
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.p1_mpwrdlctl = 0x39373f2e,
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};
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static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
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.p0_mpwldectrl0 = 0x0040003c,
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.p0_mpwldectrl1 = 0x0032003e,
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.p0_mpdgctrl0 = 0x42350231,
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.p0_mpdgctrl1 = 0x021a0218,
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.p0_mprddlctl = 0x4b4b4e49,
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.p0_mpwrdlctl = 0x3f3f3035,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF03000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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static void spl_dram_init(void)
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{
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if (is_mx6solo()) {
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mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
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mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
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} else if (is_mx6dl()) {
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mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
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mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
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} else if (is_mx6dq()) {
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mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
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mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
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}
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udelay(100);
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}
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void board_init_f(ulong dummy)
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{
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ccgr_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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gpr_init();
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/* iomux */
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board_early_init_f();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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}
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC3_BASE_ADDR},
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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/* SOM MicroSD Card Detect */
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IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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SETUP_IOMUX_PADS(usdhc3_pads);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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#endif
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
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return 0;
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else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
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return 0;
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return -EINVAL;
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}
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#endif
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