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9edefc2776
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
183 lines
4.3 KiB
C
183 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <env.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include "arm-ebi.h"
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#include "integrator-sc.h"
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#include <asm/mach-types.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct pl01x_serial_platdata serial_platdata = {
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.base = 0x16000000,
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#ifdef CONFIG_ARCH_CINTEGRATOR
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.type = TYPE_PL011,
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.clock = 14745600,
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#else
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.type = TYPE_PL010,
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.clock = 0, /* Not used for PL010 */
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#endif
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};
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U_BOOT_DEVICE(integrator_serials) = {
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.name = "serial_pl01x",
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.platdata = &serial_platdata,
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};
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void peripheral_power_enable (void);
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#if defined(CONFIG_SHOW_BOOT_PROGRESS)
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void show_boot_progress(int progress)
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{
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printf("Boot reached stage %d\n", progress);
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}
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#endif
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#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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u32 val;
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/* arch number of Integrator Board */
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#ifdef CONFIG_ARCH_CINTEGRATOR
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gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
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#else
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gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
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#endif
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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#ifdef CONFIG_CM_REMAP
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extern void cm_remap(void);
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cm_remap(); /* remaps writeable memory to 0x00000000 */
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#endif
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#ifdef CONFIG_ARCH_CINTEGRATOR
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/*
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* Flash protection on the Integrator/CP is in a simple register
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*/
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val = readl(CP_FLASHPROG);
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val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
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writel(val, CP_FLASHPROG);
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#else
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/*
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* The Integrator/AP has some special protection mechanisms
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* for the external memories, first the External Bus Interface (EBI)
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* then the system controller (SC).
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*
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* The system comes up with the flash memory non-writable and
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* configuration locked. If we want U-Boot to be used for flash
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* access we cannot have the flash memory locked.
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*/
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writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
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val = readl(EBI_BASE + EBI_CSR1_REG);
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val &= EBI_CSR_WREN_MASK;
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val |= EBI_CSR_WREN_ENABLE;
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writel(val, EBI_BASE + EBI_CSR1_REG);
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writel(0, EBI_BASE + EBI_LOCK_REG);
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/*
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* Set up the system controller to remove write protection from
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* the flash memory and enable Vpp
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*/
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writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
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#endif
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icache_enable();
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return 0;
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}
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int misc_init_r (void)
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{
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env_set("verify", "n");
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return (0);
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}
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/*
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* The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
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* from there, which means we cannot test the RAM underneath the ROM at this
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* point. It will be unmapped later on, when we are executing from the
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* relocated in RAM U-Boot. We simply assume that this RAM is usable if the
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* RAM on higher addresses works fine.
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*/
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#define REMAPPED_FLASH_SZ 0x40000
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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#ifdef CONFIG_CM_SPD_DETECT
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{
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extern void dram_query(void);
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u32 cm_reg_sdram;
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u32 sdram_shift;
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dram_query(); /* Assembler accesses to CM registers */
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/* Queries the SPD values */
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/* Obtain the SDRAM size from the CM SDRAM register */
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cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
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/* Register SDRAM size
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*
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* 0xXXXXXXbbb000bb 16 MB
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* 0xXXXXXXbbb001bb 32 MB
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* 0xXXXXXXbbb010bb 64 MB
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* 0xXXXXXXbbb011bb 128 MB
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* 0xXXXXXXbbb100bb 256 MB
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*
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*/
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sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
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gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
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REMAPPED_FLASH_SZ,
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0x01000000 << sdram_shift);
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}
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#else
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gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
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REMAPPED_FLASH_SZ,
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PHYS_SDRAM_1_SIZE);
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#endif /* CM_SPD_DETECT */
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/* We only have one bank of RAM, set it to whatever was detected */
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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rc += pci_eth_init(bis);
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return rc;
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}
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#endif
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