mirror of
https://github.com/AsahiLinux/u-boot
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149 lines
3.7 KiB
C
149 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Watchdog driver for MediaTek SoCs
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <wdt.h>
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#include <asm/io.h>
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#define MTK_WDT_MODE 0x00
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#define MTK_WDT_LENGTH 0x04
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#define MTK_WDT_RESTART 0x08
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#define MTK_WDT_STATUS 0x0c
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#define MTK_WDT_INTERVAL 0x10
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#define MTK_WDT_SWRST 0x14
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#define MTK_WDT_REQ_MODE 0x30
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#define MTK_WDT_DEBUG_CTL 0x40
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#define WDT_MODE_KEY (0x22 << 24)
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#define WDT_MODE_EN BIT(0)
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#define WDT_MODE_EXTPOL BIT(1)
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#define WDT_MODE_EXTEN BIT(2)
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#define WDT_MODE_IRQ_EN BIT(3)
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#define WDT_MODE_DUAL_EN BIT(6)
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#define WDT_LENGTH_KEY 0x8
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#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
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#define WDT_RESTART_KEY 0x1971
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#define WDT_SWRST_KEY 0x1209
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struct mtk_wdt_priv {
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void __iomem *base;
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};
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static int mtk_wdt_reset(struct udevice *dev)
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{
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struct mtk_wdt_priv *priv = dev_get_priv(dev);
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/* Reload watchdog duration */
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writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
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return 0;
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}
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static int mtk_wdt_stop(struct udevice *dev)
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{
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struct mtk_wdt_priv *priv = dev_get_priv(dev);
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clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
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return 0;
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}
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static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
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{
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struct mtk_wdt_priv *priv = dev_get_priv(dev);
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/* Kick watchdog to prevent counter == 0 */
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writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
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/* Reset */
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writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
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hang();
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return 0;
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}
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static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms)
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{
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struct mtk_wdt_priv *priv = dev_get_priv(dev);
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/*
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* One WDT_LENGTH count is 512 ticks of the wdt clock
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* Clock runs at 32768 Hz
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* e.g. 15.625 ms per count (nominal)
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* We want the ceiling after dividing timeout_ms by 15.625 ms
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* We add 15624 prior to the divide to implement the ceiling
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* We prevent over-flow by clamping the timeout_ms value here
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* as the maximum WDT_LENGTH counts is 1023 -> 15.984375 sec
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* We also enforce a minimum of 1 count
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* Many watchdog peripherals have a self-imposed count of 1
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* that is added to the register counts.
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* The MediaTek docs lack details to know if this is the case here.
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* So we enforce a minimum of 1 to guarantee operation.
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*/
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if(timeout_ms > 15984) timeout_ms = 15984;
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u64 timeout_us = timeout_ms * 1000;
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u32 timeout_cc = (u32) ( (15624 + timeout_us) / 15625 );
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if(timeout_cc == 0) timeout_cc = 1;
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u32 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
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writel(length, priv->base + MTK_WDT_LENGTH);
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}
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static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct mtk_wdt_priv *priv = dev_get_priv(dev);
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mtk_wdt_set_timeout(dev, timeout);
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mtk_wdt_reset(dev);
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/* Enable watchdog reset signal */
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setbits_le32(priv->base + MTK_WDT_MODE,
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WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
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return 0;
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}
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static int mtk_wdt_probe(struct udevice *dev)
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{
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struct mtk_wdt_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -ENOENT;
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/* Clear status */
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clrsetbits_le32(priv->base + MTK_WDT_MODE,
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WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
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return mtk_wdt_stop(dev);
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}
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static const struct wdt_ops mtk_wdt_ops = {
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.start = mtk_wdt_start,
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.reset = mtk_wdt_reset,
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.stop = mtk_wdt_stop,
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.expire_now = mtk_wdt_expire_now,
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};
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static const struct udevice_id mtk_wdt_ids[] = {
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{ .compatible = "mediatek,wdt"},
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{}
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};
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U_BOOT_DRIVER(mtk_wdt) = {
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.name = "mtk_wdt",
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.id = UCLASS_WDT,
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.of_match = mtk_wdt_ids,
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.priv_auto_alloc_size = sizeof(struct mtk_wdt_priv),
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.probe = mtk_wdt_probe,
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.ops = &mtk_wdt_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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