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https://github.com/AsahiLinux/u-boot
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75507d5d54
We now want to make sure that we have the platform data for NS16550 when we do not have OF_CONTROL set. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
277 lines
6.6 KiB
C
277 lines
6.6 KiB
C
/*
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* board.c
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*
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* Common board functions for AM33XX based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <ns16550.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <asm/errno.h>
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#include <linux/compiler.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/musb.h>
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#include <asm/omap_musb.h>
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#include <asm/davinci_rtc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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static const struct ns16550_platdata am33xx_serial[] = {
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{ CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
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# ifdef CONFIG_SYS_NS16550_COM2
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{ CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
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# ifdef CONFIG_SYS_NS16550_COM3
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{ CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
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{ CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
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{ CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
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{ CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
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# endif
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# endif
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};
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U_BOOT_DEVICES(am33xx_uarts) = {
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{ "ns16550_serial", &am33xx_serial[0] },
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# ifdef CONFIG_SYS_NS16550_COM2
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{ "ns16550_serial", &am33xx_serial[1] },
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# ifdef CONFIG_SYS_NS16550_COM3
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{ "ns16550_serial", &am33xx_serial[2] },
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{ "ns16550_serial", &am33xx_serial[3] },
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{ "ns16550_serial", &am33xx_serial[4] },
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{ "ns16550_serial", &am33xx_serial[5] },
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# endif
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# endif
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};
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#endif
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#ifndef CONFIG_DM_GPIO
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static const struct gpio_bank gpio_bank_am33xx[] = {
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{ (void *)AM33XX_GPIO0_BASE },
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{ (void *)AM33XX_GPIO1_BASE },
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{ (void *)AM33XX_GPIO2_BASE },
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{ (void *)AM33XX_GPIO3_BASE },
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#ifdef CONFIG_AM43XX
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{ (void *)AM33XX_GPIO4_BASE },
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{ (void *)AM33XX_GPIO5_BASE },
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#endif
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
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#endif
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#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
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int cpu_mmc_init(bd_t *bis)
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{
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int ret;
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ret = omap_mmc_init(0, 0, 0, -1, -1);
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if (ret)
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return ret;
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return omap_mmc_init(1, 0, 0, -1, -1);
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}
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#endif
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/* AM33XX has two MUSB controllers which can be host or gadget */
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#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
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(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* USB 2.0 PHY Control */
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#define CM_PHY_PWRDN (1 << 0)
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#define CM_PHY_OTG_PWRDN (1 << 1)
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#define OTGVDET_EN (1 << 19)
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#define OTGSESSENDEN (1 << 20)
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static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
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{
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if (on) {
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clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
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OTGVDET_EN | OTGSESSENDEN);
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} else {
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clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
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}
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}
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static struct musb_hdrc_config musb_config = {
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.multipoint = 1,
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.dyn_fifo = 1,
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.num_eps = 16,
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.ram_bits = 12,
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};
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#ifdef CONFIG_AM335X_USB0
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static void am33xx_otg0_set_phy_power(u8 on)
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{
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am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
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}
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struct omap_musb_board_data otg0_board_data = {
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.set_phy_power = am33xx_otg0_set_phy_power,
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};
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static struct musb_hdrc_platform_data otg0_plat = {
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.mode = CONFIG_AM335X_USB0_MODE,
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.config = &musb_config,
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.power = 50,
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.platform_ops = &musb_dsps_ops,
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.board_data = &otg0_board_data,
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};
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#endif
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#ifdef CONFIG_AM335X_USB1
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static void am33xx_otg1_set_phy_power(u8 on)
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{
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am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
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}
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struct omap_musb_board_data otg1_board_data = {
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.set_phy_power = am33xx_otg1_set_phy_power,
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};
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static struct musb_hdrc_platform_data otg1_plat = {
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.mode = CONFIG_AM335X_USB1_MODE,
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.config = &musb_config,
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.power = 50,
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.platform_ops = &musb_dsps_ops,
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.board_data = &otg1_board_data,
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};
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#endif
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#endif
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int arch_misc_init(void)
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{
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#ifdef CONFIG_AM335X_USB0
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musb_register(&otg0_plat, &otg0_board_data,
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(void *)USB0_OTG_BASE);
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#endif
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#ifdef CONFIG_AM335X_USB1
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musb_register(&otg1_plat, &otg1_board_data,
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(void *)USB1_OTG_BASE);
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#endif
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return 0;
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}
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* In the case of non-SPL based booting we'll want to call these
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* functions a tiny bit later as it will require gd to be set and cleared
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* and that's not true in s_init in this case so we cannot do it there.
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*/
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int board_early_init_f(void)
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{
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prcm_init();
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set_mux_conf_regs();
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return 0;
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}
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/*
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* This function is the place to do per-board things such as ramp up the
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* MPU clock frequency.
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*/
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__weak void am33xx_spl_board_init(void)
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{
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
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static void rtc32k_enable(void)
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{
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struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(RTC_KICK0R_WE, &rtc->kick0r);
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writel(RTC_KICK1R_WE, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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#endif
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static void uart_soft_reset(void)
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{
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struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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u32 regval;
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_RESET;
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writel(regval, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_SMART_IDLE_EN;
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writel(regval, &uart_base->uartsyscfg);
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}
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static void watchdog_disable(void)
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{
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struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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writel(0xAAAA, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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board_early_init_f();
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sdram_init();
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}
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#endif
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void s_init(void)
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{
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/*
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* The ROM will only have set up sufficient pinmux to allow for the
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* first 4KiB NOR to be read, we must finish doing what we know of
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* the NOR mux in this space in order to continue.
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*/
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#ifdef CONFIG_NOR_BOOT
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enable_norboot_pin_mux();
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#endif
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watchdog_disable();
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set_uart_mux_conf();
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setup_clocks_for_console();
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uart_soft_reset();
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#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
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/* Enable RTC32K clock */
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rtc32k_enable();
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#endif
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}
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#endif
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