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https://github.com/AsahiLinux/u-boot
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fff7f5e978
CONFIG_SPL_OPTEE_IMAGE option is used during DRAM size detection for Rockchip ARM platform to indicate that an OP-TEE binary was already loaded and a Trusted Execution Environment (TEE) is available in order to block/reserve a memory-region for it. This adds a bunch of new `#if's` to u-boot-rockchip.dtsi to include the OP-TEE binary in the FIT image for ARM SOCs if CONFIG_SPL_OPTEE_IMAGE is selected. That makes it a little harder to read, but I opted for that, because all the duplicates in an extra ARM-OP-TEE-specfic .dtsi would be the greater evil, IMHO. Besides it's more likley being "forgotten" to sync when changes in u-boot-rockchip.dtsi are made. The no longer required rockchip-optee.dtsi and it's inclusions are dropped. The hardcoded load address is common across all OP-TEE implemenations for Rockchip (vendor and upstream). The OP-TEE-binary is non-optional if CONFIG_SPL_OPTEE_IMAGE is selected and there will be an error if the file does not exist and/or `TEE=` build option is missing. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
136 lines
2 KiB
Text
136 lines
2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Rockchip Electronics Co., Ltd
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*/
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#include "rockchip-u-boot.dtsi"
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/ {
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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gpio5 = &gpio5;
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gpio6 = &gpio6;
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gpio7 = &gpio7;
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gpio8 = &gpio8;
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mmc0 = &emmc;
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mmc1 = &sdmmc;
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mmc2 = &sdio0;
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mmc3 = &sdio1;
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};
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chosen {
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u-boot,spl-boot-order = \
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"same-as-spl", &emmc, &sdmmc;
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};
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dmc: dmc@ff610000 {
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compatible = "rockchip,rk3288-dmc", "syscon";
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reg = <0xff610000 0x3fc
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0xff620000 0x294
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0xff630000 0x3fc
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0xff640000 0x294>;
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clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
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<&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
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<&cru ARMCLK>;
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clock-names = "pclk_ddrupctl0", "pclk_publ0",
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"pclk_ddrupctl1", "pclk_publ1",
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"arm_clk";
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rockchip,cru = <&cru>;
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rockchip,grf = <&grf>;
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rockchip,noc = <&noc>;
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rockchip,pmu = <&pmu>;
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rockchip,sgrf = <&sgrf>;
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rockchip,sram = <&ddr_sram>;
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bootph-all;
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};
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noc: syscon@ffac0000 {
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compatible = "rockchip,rk3288-noc", "syscon";
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reg = <0xffac0000 0x2000>;
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bootph-all;
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};
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};
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#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
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&binman {
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rom {
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filename = "u-boot.rom";
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size = <0x400000>;
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pad-byte = <0xff>;
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mkimage {
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args = "-n rk3288 -T rkspi";
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u-boot-spl {
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};
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};
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u-boot-img {
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offset = <0x20000>;
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};
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u-boot {
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offset = <0x300000>;
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};
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fdtmap {
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};
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};
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};
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#endif
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&bus_intmem {
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ddr_sram: ddr-sram@1000 {
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compatible = "rockchip,rk3288-ddr-sram";
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reg = <0x1000 0x4000>;
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};
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};
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&cru {
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bootph-all;
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};
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&edp {
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clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
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clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
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};
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&gpio7 {
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bootph-all;
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};
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&grf {
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bootph-all;
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};
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&pmu {
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bootph-all;
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};
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&sgrf {
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bootph-all;
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};
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&uart0 {
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clock-frequency = <24000000>;
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};
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&uart1 {
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clock-frequency = <24000000>;
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};
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&uart2 {
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clock-frequency = <24000000>;
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};
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&uart3 {
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clock-frequency = <24000000>;
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};
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&vopb {
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bootph-all;
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};
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&vopl {
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bootph-all;
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};
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