Aneesh V 882f80b993 armv7: stronger barrier for cache-maintenance operations ... set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V <aneesh@ti.com>		2011-09-04 11:36:16 +02:00
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cpu	armv7: stronger barrier for cache-maintenance operations	2011-09-04 11:36:16 +02:00
include/asm	i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c)	2011-09-04 11:36:15 +02:00
lib	arm: do not force d-cache enable on all boards	2011-09-04 11:36:16 +02:00
config.mk	arm: adjust PLATFORM_LIBS for SPL	2011-07-26 14:43:48 +02:00