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https://github.com/AsahiLinux/u-boot
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151d63cb91
Clean up mx35 lowlevel_init: - Indent with tabs. - Fix comments. - Use defined values instead of literal constants. - Use defined macros instead of duplicating code. - Use macro parameters with default values instead of #define'd configs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
139 lines
4.2 KiB
ArmAsm
139 lines
4.2 KiB
ArmAsm
/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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#include <asm/macro.h>
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/*
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* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.
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*
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* Default argument values:
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* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
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* user-mode.
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* - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
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* SDMA to access them.
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*/
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.macro init_aips mpr=0x77777777, opacr=0x00000000
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =\mpr
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str r1, [r0, #AIPS_MPR_0_7]
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str r1, [r0, #AIPS_MPR_8_15]
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ldr r2, =AIPS2_BASE_ADDR
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str r1, [r2, #AIPS_MPR_0_7]
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str r1, [r2, #AIPS_MPR_8_15]
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/* Did not change the AIPS control registers access type. */
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ldr r1, =\opacr
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str r1, [r0, #AIPS_OPACR_0_7]
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str r1, [r0, #AIPS_OPACR_8_15]
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str r1, [r0, #AIPS_OPACR_16_23]
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str r1, [r0, #AIPS_OPACR_24_31]
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str r1, [r0, #AIPS_OPACR_32_39]
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str r1, [r2, #AIPS_OPACR_0_7]
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str r1, [r2, #AIPS_OPACR_8_15]
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str r1, [r2, #AIPS_OPACR_16_23]
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str r1, [r2, #AIPS_OPACR_24_31]
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str r1, [r2, #AIPS_OPACR_32_39]
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.endm
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/*
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* MAX (Multi-Layer AHB Crossbar Switch) setup
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*
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* Default argument values:
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* - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
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* - SGPCR: always park on last master
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* - MGPCR: restore default values
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*/
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.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
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ldr r0, =MAX_BASE_ADDR
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ldr r1, =\mpr
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str r1, [r0, #MAX_MPR0] /* for S0 */
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str r1, [r0, #MAX_MPR1] /* for S1 */
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str r1, [r0, #MAX_MPR2] /* for S2 */
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str r1, [r0, #MAX_MPR3] /* for S3 */
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str r1, [r0, #MAX_MPR4] /* for S4 */
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ldr r1, =\sgpcr
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str r1, [r0, #MAX_SGPCR0] /* for S0 */
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str r1, [r0, #MAX_SGPCR1] /* for S1 */
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str r1, [r0, #MAX_SGPCR2] /* for S2 */
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str r1, [r0, #MAX_SGPCR3] /* for S3 */
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str r1, [r0, #MAX_SGPCR4] /* for S4 */
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ldr r1, =\mgpcr
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str r1, [r0, #MAX_MGPCR0] /* for M0 */
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str r1, [r0, #MAX_MGPCR1] /* for M1 */
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str r1, [r0, #MAX_MGPCR2] /* for M2 */
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str r1, [r0, #MAX_MGPCR3] /* for M3 */
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str r1, [r0, #MAX_MGPCR4] /* for M4 */
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str r1, [r0, #MAX_MGPCR5] /* for M5 */
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.endm
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/*
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* M3IF setup
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*
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* Default argument values:
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* - CTL:
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
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* ------------
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* 0x00000040
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*/
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.macro init_m3if ctl=0x00000040
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/* M3IF Control Register (M3IFCTL) */
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write32 M3IF_BASE_ADDR, \ctl
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.endm
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.macro core_init
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mrc p15, 0, r1, c1, c0, 0
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/* Set branch prediction enable */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr p15, 0, r0, c1, c0, 1
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orr r1, r1, #1 << 11
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/* Set unaligned access enable */
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orr r1, r1, #1 << 22
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/* Set low int latency enable */
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orr r1, r1, #1 << 21
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mcr p15, 0, r1, c1, c0, 0
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mov r0, #0
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mcr p15, 0, r0, c15, c2, 4
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
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mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/* Setup the Peripheral Port Memory Remap Register */
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ldr r0, =0x40000015 /* Start from AIPS 2-GB region */
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mcr p15, 0, r0, c15, c2, 4
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.endm
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