mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
02032e8f14
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
789 lines
17 KiB
ArmAsm
789 lines
17 KiB
ArmAsm
/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* U-Boot - Startup Code for PowerPC based Embedded Boards
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*
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*
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* The processor starts at 0x00000100 and the code is executed
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* from flash. The code is organized to be at an other address
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* in memory, but as long we don't jump around before relocating.
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* board_init lies at a quite high address and when the cpu has
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* jumped there, everything is ok.
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* This works because the cpu gives the FLASH (CS0) the whole
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* address space at startup, and board_init lies as a echo of
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* the flash somewhere up there in the memorymap.
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*
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* board_init will change CS0 to be positioned at the correct
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* address and (s)dram will be positioned at address 0
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*/
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#include <config.h>
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#include <mpc824x.h>
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#include <version.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING ""
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#endif
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/* We don't want the MMU yet.
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*/
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#undef MSR_KERNEL
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/* FP, Machine Check and Recoverable Interr. */
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#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI )
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/*
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* Set up GOT: Global Offset Table
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*
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* Use r14 to access the GOT
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*/
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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GOT_ENTRY(__init_end)
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GOT_ENTRY(_end)
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GOT_ENTRY(__bss_start)
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#if defined(CONFIG_FADS)
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GOT_ENTRY(environment)
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#endif
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END_GOT
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/*
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* r3 - 1st arg to board_init(): IMMP pointer
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* r4 - 2nd arg to board_init(): boot flag
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*/
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.text
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.long 0x27051956 /* U-Boot Magic Number */
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION
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.ascii " (", __DATE__, " - ", __TIME__, ")"
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.ascii CONFIG_IDENT_STRING, "\0"
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. = EXC_OFF_SYS_RESET
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.globl _start
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_start:
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li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
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b boot_cold
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. = EXC_OFF_SYS_RESET + 0x10
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.globl _start_warm
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_start_warm:
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li r21, BOOTFLAG_WARM /* Software reboot */
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b boot_warm
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boot_cold:
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boot_warm:
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/* Initialize machine status; enable machine check interrupt */
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/*----------------------------------------------------------------------*/
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li r3, MSR_KERNEL /* Set FP, ME, RI flags */
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mtmsr r3
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mtspr SRR1, r3 /* Make SRR1 match MSR */
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addis r0,0,0x0000 /* lets make sure that r0 is really 0 */
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mtspr HID0, r0 /* disable I and D caches */
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mfspr r3, ICR /* clear Interrupt Cause Register */
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mfmsr r3 /* turn off address translation */
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addis r4,0,0xffff
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ori r4,r4,0xffcf
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and r3,r3,r4
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mtmsr r3
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isync
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sync /* the MMU should be off... */
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in_flash:
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#if defined(CONFIG_BMW)
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bl early_init_f /* Must be ASM: no stack yet! */
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#endif
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/*
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* Setup BATs - cannot be done in C since we don't have a stack yet
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*/
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bl setup_bats
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/* Enable MMU.
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*/
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mfmsr r3
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ori r3, r3, (MSR_IR | MSR_DR)
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mtmsr r3
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#if !defined(CONFIG_BMW)
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/* Enable and invalidate data cache.
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*/
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mfspr r3, HID0
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mr r2, r3
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ori r3, r3, HID0_DCE | HID0_DCI
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ori r2, r2, HID0_DCE
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sync
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mtspr HID0, r3
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mtspr HID0, r2
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sync
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/* Allocate Initial RAM in data cache.
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*/
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lis r3, CFG_INIT_RAM_ADDR@h
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ori r3, r3, CFG_INIT_RAM_ADDR@l
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li r2, 128
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mtctr r2
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1:
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dcbz r0, r3
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addi r3, r3, 32
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bdnz 1b
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/* Lock way0 in data cache.
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*/
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mfspr r3, 1011
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lis r2, 0xffff
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ori r2, r2, 0xff1f
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and r3, r3, r2
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ori r3, r3, 0x0080
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sync
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mtspr 1011, r3
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#endif /* !CONFIG_BMW */
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/*
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* Thisk the stack pointer *somewhere* sensible. Doesnt
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* matter much where as we'll move it when we relocate
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*/
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lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
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ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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/* let the C-code set up the rest */
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/* */
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/* Be careful to keep code relocatable ! */
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/*----------------------------------------------------------------------*/
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GET_GOT /* initialize GOT access */
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/* r3: IMMR */
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bl cpu_init_f /* run low-level CPU init code (from Flash) */
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mr r3, r21
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/* r3: BOOTFLAG */
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bl board_init_f /* run 1st part of board init code (from Flash) */
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.globl _start_of_vectors
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_start_of_vectors:
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/* Machine check */
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STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)
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/* Data Storage exception. "Never" generated on the 860. */
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STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)
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/* Instruction Storage exception. "Never" generated on the 860. */
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STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)
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/* Alignment exception. */
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. = EXC_OFF_ALIGN
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Alignment:
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EXCEPTION_PROLOG(SRR0, SRR1)
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_Alignment:
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.long AlignmentException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* Program check exception */
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. = EXC_OFF_PROGRAM
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ProgramCheck:
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_ProgramCheck:
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.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* No FPU on MPC8xx. This exception is not supposed to happen.
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*/
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STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)
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/* I guess we could implement decrementer, and may have
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* to someday for timekeeping.
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*/
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STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
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STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
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STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
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STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
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STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)
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STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
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STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
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STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
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STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException)
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STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
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STD_EXCEPTION(0x1500, Reserved5, UnknownException)
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STD_EXCEPTION(0x1600, Reserved6, UnknownException)
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STD_EXCEPTION(0x1700, Reserved7, UnknownException)
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STD_EXCEPTION(0x1800, Reserved8, UnknownException)
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STD_EXCEPTION(0x1900, Reserved9, UnknownException)
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STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
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STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
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STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
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STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
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STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
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STD_EXCEPTION(0x1f00, ReservedF, UnknownException)
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STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)
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.globl _end_of_vectors
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_end_of_vectors:
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. = 0x3000
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/*
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* This code finishes saving the registers to the exception frame
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* and jumps to the appropriate handler for the exception.
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* Register r21 is pointer into trap frame, r1 has new stack pointer.
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*/
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.globl transfer_to_handler
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transfer_to_handler:
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stw r22,_NIP(r21)
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lis r22,MSR_POW@h
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andc r23,r23,r22
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stw r23,_MSR(r21)
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SAVE_GPR(7, r21)
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SAVE_4GPRS(8, r21)
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SAVE_8GPRS(12, r21)
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SAVE_8GPRS(24, r21)
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#if 0
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andi. r23,r23,MSR_PR
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mfspr r23,SPRG3 /* if from user, fix up tss.regs */
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beq 2f
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addi r24,r1,STACK_FRAME_OVERHEAD
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stw r24,PT_REGS(r23)
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2: addi r2,r23,-TSS /* set r2 to current */
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tovirt(r2,r2,r23)
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#endif
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mflr r23
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andi. r24,r23,0x3f00 /* get vector offset */
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stw r24,TRAP(r21)
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li r22,0
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stw r22,RESULT(r21)
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mtspr SPRG2,r22 /* r1 is now kernel sp */
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#if 0
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addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
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cmplw 0,r1,r2
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cmplw 1,r1,r24
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crand 1,1,4
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bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
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#endif
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lwz r24,0(r23) /* virtual address of handler */
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lwz r23,4(r23) /* where to go when done */
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mtspr SRR0,r24
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ori r20,r20,0x30 /* enable IR, DR */
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mtspr SRR1,r20
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mtlr r23
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SYNC
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rfi /* jump to handler, enable MMU */
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int_return:
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mfmsr r28 /* Disable interrupts */
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li r4,0
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ori r4,r4,MSR_EE
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andc r28,r28,r4
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SYNC /* Some chip revs need this... */
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mtmsr r28
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SYNC
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lwz r2,_CTR(r1)
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lwz r0,_LINK(r1)
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mtctr r2
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mtlr r0
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lwz r2,_XER(r1)
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lwz r0,_CCR(r1)
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mtspr XER,r2
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mtcrf 0xFF,r0
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REST_10GPRS(3, r1)
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REST_10GPRS(13, r1)
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REST_8GPRS(23, r1)
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REST_GPR(31, r1)
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lwz r2,_NIP(r1) /* Restore environment */
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lwz r0,_MSR(r1)
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mtspr SRR0,r2
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mtspr SRR1,r0
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lwz r0,GPR0(r1)
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lwz r2,GPR2(r1)
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lwz r1,GPR1(r1)
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SYNC
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rfi
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/* Cache functions.
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*/
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.globl icache_enable
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icache_enable:
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mfspr r5,HID0 /* turn on the I cache. */
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ori r5,r5,0x8800 /* Instruction cache only! */
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addis r6,0,0xFFFF
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ori r6,r6,0xF7FF
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and r6,r5,r6 /* clear the invalidate bit */
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sync
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mtspr HID0,r5
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mtspr HID0,r6
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isync
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sync
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blr
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.globl icache_disable
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icache_disable:
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mfspr r5,HID0
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addis r6,0,0xFFFF
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ori r6,r6,0x7FFF
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and r5,r5,r6
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sync
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mtspr HID0,r5
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isync
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sync
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blr
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.globl icache_status
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icache_status:
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mfspr r3, HID0
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srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */
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andi. r3, r3, 1
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blr
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.globl dcache_enable
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dcache_enable:
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mfspr r5,HID0 /* turn on the D cache. */
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ori r5,r5,0x4400 /* Data cache only! */
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mfspr r4, PVR /* read PVR */
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srawi r3, r4, 16 /* shift off the least 16 bits */
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cmpi 0, 0, r3, 0xC /* Check for Max pvr */
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bne NotMax
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ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */
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NotMax:
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addis r6,0,0xFFFF
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ori r6,r6,0xFBFF
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and r6,r5,r6 /* clear the invalidate bit */
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sync
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mtspr HID0,r5
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mtspr HID0,r6
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isync
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sync
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blr
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.globl dcache_disable
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dcache_disable:
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mfspr r5,HID0
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addis r6,0,0xFFFF
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ori r6,r6,0xBFFF
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and r5,r5,r6
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sync
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mtspr HID0,r5
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isync
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sync
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blr
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.globl dcache_status
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dcache_status:
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mfspr r3, HID0
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srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */
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andi. r3, r3, 1
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blr
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.globl dc_read
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dc_read:
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/*TODO : who uses this, what should it do?
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*/
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blr
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.globl get_pvr
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get_pvr:
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mfspr r3, PVR
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blr
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/*------------------------------------------------------------------------------*/
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* r3 = dest
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* r4 = src
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* r5 = length in bytes
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* r6 = cachelinesize
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*/
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.globl relocate_code
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relocate_code:
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mr r1, r3 /* Set new stack pointer */
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mr r9, r4 /* Save copy of Global Data pointer */
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mr r10, r5 /* Save copy of Destination Address */
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mr r3, r5 /* Destination Address */
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#ifdef CFG_RAMBOOT
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lis r4, CFG_SDRAM_BASE@h /* Source Address */
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ori r4, r4, CFG_SDRAM_BASE@l
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#else
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lis r4, CFG_MONITOR_BASE@h /* Source Address */
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ori r4, r4, CFG_MONITOR_BASE@l
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#endif
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lwz r5, GOT(__init_end)
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sub r5, r5, r4
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li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
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/*
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* Fix GOT pointer:
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*
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* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
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*
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* Offset:
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*/
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sub r15, r10, r4
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/* First our own GOT */
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add r14, r14, r15
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/* the the one used by the C code */
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add r30, r30, r15
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|
|
/*
|
|
* Now relocate code
|
|
*/
|
|
|
|
cmplw cr1,r3,r4
|
|
addi r0,r5,3
|
|
srwi. r0,r0,2
|
|
beq cr1,4f /* In place copy is not necessary */
|
|
beq 7f /* Protect against 0 count */
|
|
mtctr r0
|
|
bge cr1,2f
|
|
|
|
la r8,-4(r4)
|
|
la r7,-4(r3)
|
|
1: lwzu r0,4(r8)
|
|
stwu r0,4(r7)
|
|
bdnz 1b
|
|
b 4f
|
|
|
|
2: slwi r0,r0,2
|
|
add r8,r4,r0
|
|
add r7,r3,r0
|
|
3: lwzu r0,-4(r8)
|
|
stwu r0,-4(r7)
|
|
bdnz 3b
|
|
|
|
4:
|
|
#if !defined(CONFIG_BMW)
|
|
/* Unlock the data cache and invalidate locked area */
|
|
xor r0, r0, r0
|
|
mtspr 1011, r0
|
|
lis r4, CFG_INIT_RAM_ADDR@h
|
|
ori r4, r4, CFG_INIT_RAM_ADDR@l
|
|
li r0, 128
|
|
mtctr r0
|
|
41:
|
|
dcbi r0, r4
|
|
addi r4, r4, 32
|
|
bdnz 41b
|
|
#endif
|
|
|
|
/*
|
|
* Now flush the cache: note that we must start from a cache aligned
|
|
* address. Otherwise we might miss one cache line.
|
|
*/
|
|
cmpwi r6,0
|
|
add r5,r3,r5
|
|
beq 7f /* Always flush prefetch queue in any case */
|
|
subi r0,r6,1
|
|
andc r3,r3,r0
|
|
mr r4,r3
|
|
5: dcbst 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 5b
|
|
sync /* Wait for all dcbst to complete on bus */
|
|
mr r4,r3
|
|
6: icbi 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 6b
|
|
7: sync /* Wait for all icbi to complete on bus */
|
|
isync
|
|
|
|
/*
|
|
* We are done. Do not return, instead branch to second part of board
|
|
* initialization, now running from RAM.
|
|
*/
|
|
|
|
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
|
|
mtlr r0
|
|
blr
|
|
|
|
in_ram:
|
|
|
|
/*
|
|
* Relocation Function, r14 point to got2+0x8000
|
|
*
|
|
* Adjust got2 pointers, no need to check for 0, this code
|
|
* already puts a few entries in the table.
|
|
*/
|
|
li r0,__got2_entries@sectoff@l
|
|
la r3,GOT(_GOT2_TABLE_)
|
|
lwz r11,GOT(_GOT2_TABLE_)
|
|
mtctr r0
|
|
sub r11,r3,r11
|
|
addi r3,r3,-4
|
|
1: lwzu r0,4(r3)
|
|
add r0,r0,r11
|
|
stw r0,0(r3)
|
|
bdnz 1b
|
|
|
|
/*
|
|
* Now adjust the fixups and the pointers to the fixups
|
|
* in case we need to move ourselves again.
|
|
*/
|
|
2: li r0,__fixup_entries@sectoff@l
|
|
lwz r3,GOT(_FIXUP_TABLE_)
|
|
cmpwi r0,0
|
|
mtctr r0
|
|
addi r3,r3,-4
|
|
beq 4f
|
|
3: lwzu r4,4(r3)
|
|
lwzux r0,r4,r11
|
|
add r0,r0,r11
|
|
stw r10,0(r3)
|
|
stw r0,0(r4)
|
|
bdnz 3b
|
|
4:
|
|
clear_bss:
|
|
/*
|
|
* Now clear BSS segment
|
|
*/
|
|
lwz r3,GOT(__bss_start)
|
|
lwz r4,GOT(_end)
|
|
|
|
cmplw 0, r3, r4
|
|
beq 6f
|
|
|
|
li r0, 0
|
|
5:
|
|
stw r0, 0(r3)
|
|
addi r3, r3, 4
|
|
cmplw 0, r3, r4
|
|
blt 5b
|
|
6:
|
|
|
|
mr r3, r9 /* Global Data pointer */
|
|
mr r4, r10 /* Destination Address */
|
|
bl board_init_r
|
|
|
|
/*
|
|
* Copy exception vector code to low memory
|
|
*
|
|
* r3: dest_addr
|
|
* r7: source address, r8: end address, r9: target address
|
|
*/
|
|
.globl trap_init
|
|
trap_init:
|
|
lwz r7, GOT(_start)
|
|
lwz r8, GOT(_end_of_vectors)
|
|
|
|
li r9, 0x100 /* reset vector always at 0x100 */
|
|
|
|
cmplw 0, r7, r8
|
|
bgelr /* return if r7>=r8 - just in case */
|
|
|
|
mflr r4 /* save link register */
|
|
1:
|
|
lwz r0, 0(r7)
|
|
stw r0, 0(r9)
|
|
addi r7, r7, 4
|
|
addi r9, r9, 4
|
|
cmplw 0, r7, r8
|
|
bne 1b
|
|
|
|
/*
|
|
* relocate `hdlr' and `int_return' entries
|
|
*/
|
|
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
|
|
li r8, Alignment - _start + EXC_OFF_SYS_RESET
|
|
2:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 2b
|
|
|
|
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
|
|
bl trap_reloc
|
|
|
|
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
|
|
bl trap_reloc
|
|
|
|
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
|
|
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
|
|
3:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 3b
|
|
|
|
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
|
|
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
|
|
4:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 4b
|
|
|
|
mtlr r4 /* restore link register */
|
|
blr
|
|
|
|
/*
|
|
* Function: relocate entries for one exception vector
|
|
*/
|
|
trap_reloc:
|
|
lwz r0, 0(r7) /* hdlr ... */
|
|
add r0, r0, r3 /* ... += dest_addr */
|
|
stw r0, 0(r7)
|
|
|
|
lwz r0, 4(r7) /* int_return ... */
|
|
add r0, r0, r3 /* ... += dest_addr */
|
|
stw r0, 4(r7)
|
|
|
|
blr
|
|
|
|
/* Setup the BAT registers.
|
|
*/
|
|
setup_bats:
|
|
lis r4, CFG_IBAT0L@h
|
|
ori r4, r4, CFG_IBAT0L@l
|
|
lis r3, CFG_IBAT0U@h
|
|
ori r3, r3, CFG_IBAT0U@l
|
|
mtspr IBAT0L, r4
|
|
mtspr IBAT0U, r3
|
|
isync
|
|
|
|
lis r4, CFG_DBAT0L@h
|
|
ori r4, r4, CFG_DBAT0L@l
|
|
lis r3, CFG_DBAT0U@h
|
|
ori r3, r3, CFG_DBAT0U@l
|
|
mtspr DBAT0L, r4
|
|
mtspr DBAT0U, r3
|
|
isync
|
|
|
|
lis r4, CFG_IBAT1L@h
|
|
ori r4, r4, CFG_IBAT1L@l
|
|
lis r3, CFG_IBAT1U@h
|
|
ori r3, r3, CFG_IBAT1U@l
|
|
mtspr IBAT1L, r4
|
|
mtspr IBAT1U, r3
|
|
isync
|
|
|
|
lis r4, CFG_DBAT1L@h
|
|
ori r4, r4, CFG_DBAT1L@l
|
|
lis r3, CFG_DBAT1U@h
|
|
ori r3, r3, CFG_DBAT1U@l
|
|
mtspr DBAT1L, r4
|
|
mtspr DBAT1U, r3
|
|
isync
|
|
|
|
lis r4, CFG_IBAT2L@h
|
|
ori r4, r4, CFG_IBAT2L@l
|
|
lis r3, CFG_IBAT2U@h
|
|
ori r3, r3, CFG_IBAT2U@l
|
|
mtspr IBAT2L, r4
|
|
mtspr IBAT2U, r3
|
|
isync
|
|
|
|
lis r4, CFG_DBAT2L@h
|
|
ori r4, r4, CFG_DBAT2L@l
|
|
lis r3, CFG_DBAT2U@h
|
|
ori r3, r3, CFG_DBAT2U@l
|
|
mtspr DBAT2L, r4
|
|
mtspr DBAT2U, r3
|
|
isync
|
|
|
|
lis r4, CFG_IBAT3L@h
|
|
ori r4, r4, CFG_IBAT3L@l
|
|
lis r3, CFG_IBAT3U@h
|
|
ori r3, r3, CFG_IBAT3U@l
|
|
mtspr IBAT3L, r4
|
|
mtspr IBAT3U, r3
|
|
isync
|
|
|
|
lis r4, CFG_DBAT3L@h
|
|
ori r4, r4, CFG_DBAT3L@l
|
|
lis r3, CFG_DBAT3U@h
|
|
ori r3, r3, CFG_DBAT3U@l
|
|
mtspr DBAT3L, r4
|
|
mtspr DBAT3U, r3
|
|
isync
|
|
|
|
/* Invalidate TLBs.
|
|
* -> for (val = 0; val < 0x20000; val+=0x1000)
|
|
* -> tlbie(val);
|
|
*/
|
|
lis r3, 0
|
|
lis r5, 2
|
|
|
|
1:
|
|
tlbie r3
|
|
addi r3, r3, 0x1000
|
|
cmp 0, 0, r3, r5
|
|
blt 1b
|
|
|
|
blr
|