mirror of
https://github.com/AsahiLinux/u-boot
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eac3bbe5d8
Add QSPI driver code for the Microchip PolarFire SoC. This driver supports the QSPI standard, dual and quad mode interfaces. Co-developed-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
505 lines
14 KiB
C
505 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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* Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* QSPI Control register mask defines
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*/
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#define CONTROL_ENABLE BIT(0)
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#define CONTROL_MASTER BIT(1)
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#define CONTROL_XIP BIT(2)
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#define CONTROL_XIPADDR BIT(3)
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#define CONTROL_CLKIDLE BIT(10)
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#define CONTROL_SAMPLE_MASK GENMASK(12, 11)
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#define CONTROL_MODE0 BIT(13)
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#define CONTROL_MODE12_MASK GENMASK(15, 14)
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#define CONTROL_MODE12_EX_RO BIT(14)
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#define CONTROL_MODE12_EX_RW BIT(15)
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#define CONTROL_MODE12_FULL GENMASK(15, 14)
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#define CONTROL_FLAGSX4 BIT(16)
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#define CONTROL_CLKRATE_MASK GENMASK(27, 24)
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#define CONTROL_CLKRATE_SHIFT 24
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/*
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* QSPI Frames register mask defines
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*/
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#define FRAMES_TOTALBYTES_MASK GENMASK(15, 0)
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#define FRAMES_CMDBYTES_MASK GENMASK(24, 16)
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#define FRAMES_CMDBYTES_SHIFT 16
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#define FRAMES_SHIFT 25
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#define FRAMES_IDLE_MASK GENMASK(29, 26)
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#define FRAMES_IDLE_SHIFT 26
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#define FRAMES_FLAGBYTE BIT(30)
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#define FRAMES_FLAGWORD BIT(31)
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/*
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* QSPI Interrupt Enable register mask defines
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*/
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#define IEN_TXDONE BIT(0)
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#define IEN_RXDONE BIT(1)
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#define IEN_RXAVAILABLE BIT(2)
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#define IEN_TXAVAILABLE BIT(3)
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#define IEN_RXFIFOEMPTY BIT(4)
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#define IEN_TXFIFOFULL BIT(5)
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/*
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* QSPI Status register mask defines
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*/
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#define STATUS_TXDONE BIT(0)
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#define STATUS_RXDONE BIT(1)
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#define STATUS_RXAVAILABLE BIT(2)
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#define STATUS_TXAVAILABLE BIT(3)
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#define STATUS_RXFIFOEMPTY BIT(4)
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#define STATUS_TXFIFOFULL BIT(5)
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#define STATUS_READY BIT(7)
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#define STATUS_FLAGSX4 BIT(8)
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#define STATUS_MASK GENMASK(8, 0)
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#define BYTESUPPER_MASK GENMASK(31, 16)
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#define BYTESLOWER_MASK GENMASK(15, 0)
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#define MAX_DIVIDER 16
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#define MIN_DIVIDER 0
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#define MAX_DATA_CMD_LEN 256
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/* QSPI ready time out value */
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#define TIMEOUT_MS (1000 * 500)
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/*
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* QSPI Register offsets.
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*/
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#define REG_CONTROL (0x00)
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#define REG_FRAMES (0x04)
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#define REG_IEN (0x0c)
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#define REG_STATUS (0x10)
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#define REG_DIRECT_ACCESS (0x14)
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#define REG_UPPER_ACCESS (0x18)
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#define REG_RX_DATA (0x40)
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#define REG_TX_DATA (0x44)
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#define REG_X4_RX_DATA (0x48)
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#define REG_X4_TX_DATA (0x4c)
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#define REG_FRAMESUP (0x50)
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/**
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* struct mchp_coreqspi - Defines qspi driver instance
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* @regs: Address of the QSPI controller registers
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* @freq: QSPI Input frequency
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* @txbuf: TX buffer
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* @rxbuf: RX buffer
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* @tx_len: Number of bytes left to transfer
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* @rx_len: Number of bytes left to receive
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*/
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struct mchp_coreqspi {
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void __iomem *regs;
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u32 freq;
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u8 *txbuf;
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u8 *rxbuf;
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int tx_len;
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int rx_len;
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};
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static void mchp_coreqspi_init_hw(struct mchp_coreqspi *qspi)
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{
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u32 control;
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control = CONTROL_CLKIDLE | CONTROL_ENABLE;
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writel(control, qspi->regs + REG_CONTROL);
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writel(0, qspi->regs + REG_IEN);
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}
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static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi)
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{
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u32 control, data;
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if (!qspi->rx_len)
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return;
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control = readl(qspi->regs + REG_CONTROL);
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/*
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* Read 4-bytes from the SPI FIFO in single transaction and then read
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* the reamaining data byte wise.
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*/
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control |= CONTROL_FLAGSX4;
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writel(control, qspi->regs + REG_CONTROL);
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while (qspi->rx_len >= 4) {
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while (readl(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
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;
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data = readl(qspi->regs + REG_X4_RX_DATA);
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*(u32 *)qspi->rxbuf = data;
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qspi->rxbuf += 4;
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qspi->rx_len -= 4;
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}
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control &= ~CONTROL_FLAGSX4;
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writel(control, qspi->regs + REG_CONTROL);
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while (qspi->rx_len--) {
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while (readl(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
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;
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data = readl(qspi->regs + REG_RX_DATA);
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*qspi->rxbuf++ = (data & 0xFF);
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}
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}
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static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word)
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{
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u32 control, data;
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control = readl(qspi->regs + REG_CONTROL);
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control |= CONTROL_FLAGSX4;
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writel(control, qspi->regs + REG_CONTROL);
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while (qspi->tx_len >= 4) {
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while (readl(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
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;
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data = *(u32 *)qspi->txbuf;
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qspi->txbuf += 4;
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qspi->tx_len -= 4;
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writel(data, qspi->regs + REG_X4_TX_DATA);
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}
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control &= ~CONTROL_FLAGSX4;
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writel(control, qspi->regs + REG_CONTROL);
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while (qspi->tx_len--) {
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while (readl(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
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;
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data = *qspi->txbuf++;
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writel(data, qspi->regs + REG_TX_DATA);
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}
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}
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static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi,
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const struct spi_mem_op *op)
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{
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u32 idle_cycles = 0;
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int total_bytes, cmd_bytes, frames, ctrl;
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cmd_bytes = op->cmd.nbytes + op->addr.nbytes;
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total_bytes = cmd_bytes + op->data.nbytes;
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/*
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* As per the coreQSPI IP spec,the number of command and data bytes are
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* controlled by the frames register for each SPI sequence. This supports
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* the SPI flash memory read and writes sequences as below. so configure
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* the cmd and total bytes accordingly.
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* ---------------------------------------------------------------------
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* TOTAL BYTES | CMD BYTES | What happens |
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* ______________________________________________________________________
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* | | |
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* 1 | 1 | The SPI core will transmit a single byte |
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* | | and receive data is discarded |
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* | | |
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* 1 | 0 | The SPI core will transmit a single byte |
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* | | and return a single byte |
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* | | |
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* 10 | 4 | The SPI core will transmit 4 command |
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* | | bytes discarding the receive data and |
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* | | transmits 6 dummy bytes returning the 6 |
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* | | received bytes and return a single byte |
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* | | |
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* 10 | 10 | The SPI core will transmit 10 command |
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* | | |
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* 10 | 0 | The SPI core will transmit 10 command |
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* | | bytes and returning 10 received bytes |
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* ______________________________________________________________________
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*/
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if (!(op->data.dir == SPI_MEM_DATA_IN))
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cmd_bytes = total_bytes;
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frames = total_bytes & BYTESUPPER_MASK;
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writel(frames, qspi->regs + REG_FRAMESUP);
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frames = total_bytes & BYTESLOWER_MASK;
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frames |= cmd_bytes << FRAMES_CMDBYTES_SHIFT;
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if (op->dummy.buswidth)
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idle_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
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frames |= idle_cycles << FRAMES_IDLE_SHIFT;
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ctrl = readl(qspi->regs + REG_CONTROL);
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if (ctrl & CONTROL_MODE12_MASK)
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frames |= (1 << FRAMES_SHIFT);
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frames |= FRAMES_FLAGWORD;
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writel(frames, qspi->regs + REG_FRAMES);
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}
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static int mchp_coreqspi_wait_for_ready(struct spi_slave *slave)
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{
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struct mchp_coreqspi *qspi = dev_get_priv(slave->dev->parent);
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unsigned long count = 0;
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while (1) {
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if (readl(qspi->regs + REG_STATUS) & STATUS_READY)
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return 0;
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udelay(1);
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count += 1;
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if (count == TIMEOUT_MS)
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return -ETIMEDOUT;
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}
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}
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static int mchp_coreqspi_set_operate_mode(struct mchp_coreqspi *qspi,
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const struct spi_mem_op *op)
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{
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u32 control = readl(qspi->regs + REG_CONTROL);
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/*
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* The operating mode can be configured based on the command that needs
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* to be send.
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* bits[15:14]: Sets whether multiple bit SPI operates in normal,
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* extended or full modes.
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* 00: Normal (single DQ0 TX and single DQ1 RX lines)
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* 01: Extended RO (command and address bytes on DQ0 only)
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* 10: Extended RW (command byte on DQ0 only)
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* 11: Full. (command and address are on all DQ lines)
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* bit[13]: Sets whether multiple bit SPI uses 2 or 4 bits of data
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* 0: 2-bits (BSPI)
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* 1: 4-bits (QSPI)
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*/
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if (op->data.buswidth == 4 || op->data.buswidth == 2) {
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control &= ~CONTROL_MODE12_MASK;
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if (op->cmd.buswidth == 1 && (op->addr.buswidth == 1 ||
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op->addr.buswidth == 0))
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control |= CONTROL_MODE12_EX_RO;
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else if (op->cmd.buswidth == 1)
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control |= CONTROL_MODE12_EX_RW;
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else
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control |= CONTROL_MODE12_FULL;
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control |= CONTROL_MODE0;
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} else {
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control &= ~(CONTROL_MODE12_MASK | CONTROL_MODE0);
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}
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writel(control, qspi->regs + REG_CONTROL);
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return 0;
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}
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static int mchp_coreqspi_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct mchp_coreqspi *qspi = dev_get_priv(slave->dev->parent);
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u32 address = op->addr.val;
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u8 opcode = op->cmd.opcode;
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u8 opaddr[5];
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int err = 0, i;
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err = mchp_coreqspi_wait_for_ready(slave);
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if (err)
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return err;
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err = mchp_coreqspi_set_operate_mode(qspi, op);
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if (err)
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return err;
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mchp_coreqspi_config_op(qspi, op);
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if (op->cmd.opcode) {
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qspi->txbuf = &opcode;
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qspi->rxbuf = NULL;
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qspi->tx_len = op->cmd.nbytes;
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qspi->rx_len = 0;
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mchp_coreqspi_write_op(qspi, false);
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}
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qspi->txbuf = &opaddr[0];
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if (op->addr.nbytes) {
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for (i = 0; i < op->addr.nbytes; i++)
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qspi->txbuf[i] = address >> (8 * (op->addr.nbytes - i - 1));
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qspi->rxbuf = NULL;
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qspi->tx_len = op->addr.nbytes;
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qspi->rx_len = 0;
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mchp_coreqspi_write_op(qspi, false);
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}
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_OUT) {
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qspi->txbuf = (u8 *)op->data.buf.out;
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qspi->rxbuf = NULL;
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qspi->rx_len = 0;
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qspi->tx_len = op->data.nbytes;
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mchp_coreqspi_write_op(qspi, true);
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} else {
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qspi->txbuf = NULL;
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qspi->rxbuf = (u8 *)op->data.buf.in;
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qspi->rx_len = op->data.nbytes;
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qspi->tx_len = 0;
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mchp_coreqspi_read_op(qspi);
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}
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}
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return 0;
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}
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static bool mchp_coreqspi_supports_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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if (!spi_mem_default_supports_op(slave, op))
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return false;
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if ((op->data.buswidth == 4 || op->data.buswidth == 2) &&
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(op->cmd.buswidth == 1 && (op->addr.buswidth == 1 ||
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op->addr.buswidth == 0))) {
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/*
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* If the command and address are on DQ0 only, then this
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* controller doesn't support sending data on dual and
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* quad lines. but it supports reading data on dual and
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* quad lines with same configuration as command and
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* address on DQ0.
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* i.e. The control register[15:13] :EX_RO(read only) is
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* meant only for the command and address are on DQ0 but
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* not to write data, it is just to read.
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* Ex: 0x34h is Quad Load Program Data which is not
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* supported. Then the spi-mem layer will iterate over
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* each command and it will chose the supported one.
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*/
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if (op->data.dir == SPI_MEM_DATA_OUT)
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return false;
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}
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return true;
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}
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static int mchp_coreqspi_adjust_op_size(struct spi_slave *slave,
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struct spi_mem_op *op)
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{
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if (op->data.dir == SPI_MEM_DATA_OUT) {
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if (op->data.nbytes > MAX_DATA_CMD_LEN)
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op->data.nbytes = MAX_DATA_CMD_LEN;
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}
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return 0;
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}
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static int mchp_coreqspi_set_speed(struct udevice *dev, uint speed)
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{
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struct mchp_coreqspi *qspi = dev_get_priv(dev);
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u32 control, baud_rate_val = 0;
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if (speed > (qspi->freq / 2))
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speed = qspi->freq / 2;
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baud_rate_val = DIV_ROUND_UP(qspi->freq, 2 * speed);
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if (baud_rate_val >= MAX_DIVIDER || baud_rate_val <= MIN_DIVIDER)
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return -EINVAL;
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control = readl(qspi->regs + REG_CONTROL);
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control &= ~CONTROL_CLKRATE_MASK;
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control |= baud_rate_val << CONTROL_CLKRATE_SHIFT;
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writel(control, qspi->regs + REG_CONTROL);
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return 0;
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}
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static int mchp_coreqspi_set_mode(struct udevice *dev, uint mode)
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{
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struct mchp_coreqspi *qspi = dev_get_priv(dev);
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u32 control;
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control = readl(qspi->regs + REG_CONTROL);
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if ((mode & SPI_CPOL) && (mode & SPI_CPHA))
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control |= CONTROL_CLKIDLE;
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else
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control &= ~CONTROL_CLKIDLE;
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writel(control, qspi->regs + REG_CONTROL);
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return 0;
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}
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static int mchp_coreqspi_claim_bus(struct udevice *dev)
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{
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return 0;
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}
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static int mchp_coreqspi_release_bus(struct udevice *dev)
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{
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return 0;
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}
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static int mchp_coreqspi_probe(struct udevice *dev)
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{
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struct mchp_coreqspi *qspi = dev_get_priv(dev);
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struct clk clk;
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ulong clk_rate;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return -EINVAL;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&clk);
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if (!clk_rate)
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return -EINVAL;
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qspi->freq = clk_rate;
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qspi->regs = dev_read_addr_ptr(dev);
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if (!qspi->regs)
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return -EINVAL;
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/* Init the mpfs qspi hw */
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mchp_coreqspi_init_hw(qspi);
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return 0;
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}
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static const struct spi_controller_mem_ops mchp_coreqspi_mem_ops = {
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.adjust_op_size = mchp_coreqspi_adjust_op_size,
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.supports_op = mchp_coreqspi_supports_op,
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.exec_op = mchp_coreqspi_exec_op,
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};
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static const struct dm_spi_ops mchp_coreqspi_ops = {
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.claim_bus = mchp_coreqspi_claim_bus,
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.release_bus = mchp_coreqspi_release_bus,
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.set_speed = mchp_coreqspi_set_speed,
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.set_mode = mchp_coreqspi_set_mode,
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.mem_ops = &mchp_coreqspi_mem_ops,
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};
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static const struct udevice_id mchp_coreqspi_ids[] = {
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{ .compatible = "microchip,mpfs-coreqspi-rtl-v2" },
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{ .compatible = "microchip,mpfs-qspi" },
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{ }
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};
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U_BOOT_DRIVER(mchp_coreqspi) = {
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.name = "mchp_coreqspi",
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.id = UCLASS_SPI,
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.of_match = mchp_coreqspi_ids,
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.ops = &mchp_coreqspi_ops,
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.priv_auto = sizeof(struct mchp_coreqspi),
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.probe = mchp_coreqspi_probe,
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};
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