mirror of
https://github.com/AsahiLinux/u-boot
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7a2aa8b681
v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
355 lines
11 KiB
C
355 lines
11 KiB
C
/*
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*
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* Common board functions for OMAP3 based boards.
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*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/cache.h>
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extern omap3_sysinfo sysinfo;
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extern u32 is_mem_sdr(void);
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/******************************************************************************
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* Routine: delay
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* Description: spinning delay to use before udelay works
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*****************************************************************************/
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static inline void delay(unsigned long loops)
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{
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__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0"(loops));
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}
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/******************************************************************************
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* Routine: secure_unlock
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* Description: Setup security registers for access
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* (GP Device only)
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*****************************************************************************/
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void secure_unlock_mem(void)
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{
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struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
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struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
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struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
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struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
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struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
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/* Protection Module Register Target APE (PM_RT) */
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writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
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writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
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writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
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writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
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writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
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writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
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writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
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writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
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writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
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writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
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writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
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/* IVA Changes */
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writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
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writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
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writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
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/* SDRC region 0 public */
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writel(UNLOCK_1, &sms_base->rg_att0);
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}
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/******************************************************************************
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* Routine: secureworld_exit()
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* Description: If chip is EMU and boot type is external
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* configure secure registers and exit secure world
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* general use.
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*****************************************************************************/
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void secureworld_exit()
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{
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unsigned long i;
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/* configrue non-secure access control register */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
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/* enabling co-processor CP10 and CP11 accesses in NS world */
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__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
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/*
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* allow allocation of locked TLBs and L2 lines in NS world
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* allow use of PLE registers in NS world also
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*/
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__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
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/* Enable ASA in ACR register */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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/* Exiting secure world */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
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}
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/******************************************************************************
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* Routine: setup_auxcr()
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* Description: Write to AuxCR desired value using SMI.
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* general use.
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*****************************************************************************/
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void setup_auxcr()
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{
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unsigned long i;
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volatile unsigned int j;
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/* Save r0, r12 and restore them after usage */
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__asm__ __volatile__("mov %0, r12":"=r"(j));
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__asm__ __volatile__("mov %0, r0":"=r"(i));
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/*
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* GP Device ROM code API usage here
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* r12 = AUXCR Write function and r0 value
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*/
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__asm__ __volatile__("mov r12, #0x3");
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__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
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/* Enabling ASA */
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__asm__ __volatile__("orr r0, r0, #0x10");
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/* Enable L1NEON */
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__asm__ __volatile__("orr r0, r0, #1 << 5");
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/* SMI instruction to call ROM Code API */
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__asm__ __volatile__(".word 0xE1600070");
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__asm__ __volatile__("mov r0, %0":"=r"(i));
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__asm__ __volatile__("mov r12, %0":"=r"(j));
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}
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/******************************************************************************
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* Routine: try_unlock_sram()
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* Description: If chip is GP/EMU(special) type, unlock the SRAM for
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* general use.
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*****************************************************************************/
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void try_unlock_memory()
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{
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int mode;
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int in_sdram = is_running_in_sdram();
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/*
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* if GP device unlock device SRAM for general use
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* secure code breaks for Secure/Emulation device - HS/E/T
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*/
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mode = get_device_type();
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if (mode == GP_DEVICE)
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secure_unlock_mem();
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/*
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* If device is EMU and boot is XIP external booting
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* Unlock firewalls and disable L2 and put chip
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* out of secure world
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*
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* Assuming memories are unlocked by the demon who put us in SDRAM
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*/
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if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
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&& (!in_sdram)) {
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secure_unlock_mem();
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secureworld_exit();
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}
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return;
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}
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/******************************************************************************
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* Routine: s_init
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* Description: Does early system init of muxing and clocks.
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* - Called path is with SRAM stack.
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*****************************************************************************/
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void s_init(void)
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{
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int in_sdram = is_running_in_sdram();
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watchdog_init();
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try_unlock_memory();
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/*
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* Right now flushing at low MPU speed.
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* Need to move after clock init
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*/
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invalidate_dcache(get_device_type());
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#ifndef CONFIG_ICACHE_OFF
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icache_enable();
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#endif
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#ifdef CONFIG_L2_OFF
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l2_cache_disable();
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#else
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l2_cache_enable();
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#endif
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/*
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* Writing to AuxCR in U-boot using SMI for GP DEV
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* Currently SMI in Kernel on ES2 devices seems to have an issue
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* Once that is resolved, we can postpone this config to kernel
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*/
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if (get_device_type() == GP_DEVICE)
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setup_auxcr();
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set_muxconf_regs();
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delay(100);
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prcm_init();
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per_clocks_enable();
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if (!in_sdram)
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sdrc_init();
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}
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/******************************************************************************
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* Routine: wait_for_command_complete
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* Description: Wait for posting to finish on watchdog
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*****************************************************************************/
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void wait_for_command_complete(struct watchdog *wd_base)
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{
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int pending = 1;
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do {
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pending = readl(&wd_base->wwps);
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} while (pending);
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}
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/******************************************************************************
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* Routine: watchdog_init
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* Description: Shut down watch dogs
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*****************************************************************************/
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void watchdog_init(void)
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{
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struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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/*
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* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
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* either taken care of by ROM (HS/EMU) or not accessible (GP).
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* We need to take care of WD2-MPU or take a PRCM reset. WD3
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* should not be running and does not generate a PRCM reset.
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*/
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sr32(&prcm_base->fclken_wkup, 5, 1, 1);
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sr32(&prcm_base->iclken_wkup, 5, 1, 1);
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wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
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writel(WD_UNLOCK1, &wd2_base->wspr);
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wait_for_command_complete(wd2_base);
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writel(WD_UNLOCK2, &wd2_base->wspr);
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}
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/******************************************************************************
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* Routine: dram_init
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* Description: sets uboots idea of sdram size
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*****************************************************************************/
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int size0 = 0, size1 = 0;
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/*
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* If a second bank of DDR is attached to CS1 this is
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* where it can be started. Early init code will init
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* memory on CS0.
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*/
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if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
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do_sdrc_init(CS1, NOT_EARLY);
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make_cs1_contiguous();
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}
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size0 = get_sdr_cs_size(CS0);
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size1 = get_sdr_cs_size(CS1);
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = size0;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
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gd->bd->bi_dram[1].size = size1;
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return 0;
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}
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/******************************************************************************
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* Dummy function to handle errors for EABI incompatibility
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*****************************************************************************/
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void abort(void)
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{
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}
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#ifdef CONFIG_NAND_OMAP_GPMC
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/******************************************************************************
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* OMAP3 specific command to switch between NAND HW and SW ecc
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*****************************************************************************/
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static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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if (argc != 2)
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goto usage;
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if (strncmp(argv[1], "hw", 2) == 0)
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omap_nand_switch_ecc(1);
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else if (strncmp(argv[1], "sw", 2) == 0)
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omap_nand_switch_ecc(0);
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else
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goto usage;
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return 0;
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usage:
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printf ("Usage: nandecc %s\n", cmdtp->usage);
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return 1;
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}
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U_BOOT_CMD(
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nandecc, 2, 1, do_switch_ecc,
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"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
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"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
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);
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#endif /* CONFIG_NAND_OMAP_GPMC */
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#ifdef CONFIG_DISPLAY_BOARDINFO
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/**
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* Print board information
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*/
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int checkboard (void)
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{
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char *mem_s ;
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if (is_mem_sdr())
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mem_s = "mSDR";
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else
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mem_s = "LPDDR";
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printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
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sysinfo.nand_string);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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