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https://github.com/AsahiLinux/u-boot
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879f9fed6a
Add simplified and meaningful macro for all setting. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (Squash the similar patches into 1 patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
132 lines
3.5 KiB
C
132 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _ASM_ARCH_SDRAM_COMMON_H
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#define _ASM_ARCH_SDRAM_COMMON_H
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enum {
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DDR4 = 0,
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DDR3 = 0x3,
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LPDDR2 = 0x5,
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LPDDR3 = 0x6,
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LPDDR4 = 0x7,
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UNUSED = 0xFF
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};
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struct sdram_cap_info {
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unsigned int rank;
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/* dram column number, 0 means this channel is invalid */
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unsigned int col;
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/* dram bank number, 3:8bank, 2:4bank */
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unsigned int bk;
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/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned int bw;
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/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned int dbw;
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/*
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* row_3_4 = 1: 6Gb or 12Gb die
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* row_3_4 = 0: normal die, power of 2
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*/
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unsigned int row_3_4;
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unsigned int cs0_row;
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unsigned int cs1_row;
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unsigned int ddrconfig;
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};
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struct sdram_base_params {
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unsigned int ddr_freq;
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unsigned int dramtype;
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unsigned int num_channels;
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unsigned int stride;
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unsigned int odt;
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};
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/*
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* sys_reg bitfield struct
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* [31] row_3_4_ch1
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* [30] row_3_4_ch0
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* [29:28] chinfo
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* [27] rank_ch1
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* [26:25] col_ch1
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* [24] bk_ch1
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* [23:22] cs0_row_ch1
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* [21:20] cs1_row_ch1
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* [19:18] bw_ch1
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* [17:16] dbw_ch1;
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* [15:13] ddrtype
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* [12] channelnum
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* [11] rank_ch0
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* [10:9] col_ch0
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* [8] bk_ch0
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* [7:6] cs0_row_ch0
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* [5:4] cs1_row_ch0
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* [3:2] bw_ch0
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* [1:0] dbw_ch0
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*/
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#define SYS_REG_DDRTYPE_SHIFT 13
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#define SYS_REG_DDRTYPE_MASK 7
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#define SYS_REG_NUM_CH_SHIFT 12
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#define SYS_REG_NUM_CH_MASK 1
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#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
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#define SYS_REG_ROW_3_4_MASK 1
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#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
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#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
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#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
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#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT)
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#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \
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SYS_REG_NUM_CH_SHIFT)
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#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
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#define SYS_REG_RANK_MASK 1
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#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
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SYS_REG_RANK_SHIFT(ch))
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#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
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#define SYS_REG_COL_MASK 3
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#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
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#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
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#define SYS_REG_BK_MASK 1
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#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
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SYS_REG_BK_SHIFT(ch))
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#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
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#define SYS_REG_CS0_ROW_MASK 3
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#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \
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SYS_REG_CS0_ROW_SHIFT(ch))
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#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
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#define SYS_REG_CS1_ROW_MASK 3
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#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \
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SYS_REG_CS1_ROW_SHIFT(ch))
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#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
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#define SYS_REG_BW_MASK 3
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#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
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#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
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#define SYS_REG_DBW_MASK 3
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#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
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/* Get sdram size decode from reg */
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size_t rockchip_sdram_size(phys_addr_t reg);
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/* Called by U-Boot board_init_r for Rockchip SoCs */
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int dram_init(void);
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#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
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inline void sdram_print_dram_type(unsigned char dramtype)
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{
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}
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inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base)
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{
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}
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inline void sdram_print_stride(unsigned int stride)
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{
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}
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#else
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void sdram_print_dram_type(unsigned char dramtype);
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void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base);
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void sdram_print_stride(unsigned int stride);
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#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
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#endif
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