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543 lines
13 KiB
C
543 lines
13 KiB
C
/**
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* @file QMgrQCfg.c
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*
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* @author Intel Corporation
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* @date 30-Oct-2001
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*
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* @brief This modules provides an interface for setting up the static
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* configuration of AQM queues.This file contains the following
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* functions:
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*
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/*
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* System defined include files.
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*/
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/*
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* User defined include files.
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*/
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#include "IxOsal.h"
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#include "IxQMgr.h"
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#include "IxQMgrAqmIf_p.h"
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#include "IxQMgrQCfg_p.h"
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#include "IxQMgrDefines_p.h"
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/*
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* #defines and macros used in this file.
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*/
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#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
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/* Total size of SRAM */
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#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
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/*
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* Check that qId is a valid queue identifier. This is provided to
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* make the code easier to read.
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*/
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#define IX_QMGR_QID_IS_VALID(qId) \
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(((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID)))
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/*
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* Typedefs whose scope is limited to this file.
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*/
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/*
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* This struct describes an AQM queue.
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* N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue
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* as these are requested by Access in the data path. sizeInEntries is
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* not required by the data path so it can be calculated dynamically.
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*
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*/
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typedef struct
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{
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char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/
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IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */
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IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/
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BOOL isConfigured; /* This flag is TRUE if the queue has
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* been configured
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*/
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} IxQMgrCfgQ;
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/*
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* Variable declarations global to this file. Externs are followed by
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* statics.
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*/
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extern UINT32 * ixQMgrAqmIfQueAccRegAddr[];
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/* Store data required to inline read and write access
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*/
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IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES];
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static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES];
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/* This pointer holds the starting address of AQM SRAM not used by
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* the AQM queues.
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*/
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static UINT32 freeSramAddress=0;
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/* 4 words of zeroed memory for inline access */
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static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 };
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static BOOL cfgInitialized = FALSE;
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static IxOsalMutex ixQMgrQCfgMutex;
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/*
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* Statistics
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*/
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static IxQMgrQCfgStats stats;
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/*
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* Function declarations
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*/
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PRIVATE BOOL
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watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level);
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PRIVATE BOOL
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qSizeInWordsIsOk (IxQMgrQSizeInWords qSize);
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PRIVATE BOOL
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qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize);
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/*
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* Function definitions.
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*/
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void
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ixQMgrQCfgInit (void)
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{
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int loopIndex;
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for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
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{
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/* info for code inlining */
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ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder;
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/* info for code inlining */
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ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0;
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ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0;
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ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder;
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ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder;
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ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0;
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ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0;
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ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0;
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ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0;
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ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder;
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}
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/* Initialise the AqmIf component */
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ixQMgrAqmIfInit ();
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/* Reset all queues to have queue name = NULL, entry size = 0 and
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* isConfigured = false
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*/
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for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
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{
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strcpy (cfgQueueInfo[loopIndex].qName, "");
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cfgQueueInfo[loopIndex].qSizeInWords = 0;
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cfgQueueInfo[loopIndex].qEntrySizeInWords = 0;
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cfgQueueInfo[loopIndex].isConfigured = FALSE;
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/* Statistics */
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stats.qStats[loopIndex].isConfigured = FALSE;
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stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName;
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}
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/* Statistics */
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stats.wmSetCnt = 0;
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ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress);
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ixOsalMutexInit(&ixQMgrQCfgMutex);
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cfgInitialized = TRUE;
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}
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void
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ixQMgrQCfgUninit (void)
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{
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cfgInitialized = FALSE;
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/* Uninitialise the AqmIf component */
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ixQMgrAqmIfUninit ();
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}
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IX_STATUS
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ixQMgrQConfig (char *qName,
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IxQMgrQId qId,
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IxQMgrQSizeInWords qSizeInWords,
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IxQMgrQEntrySizeInWords qEntrySizeInWords)
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{
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UINT32 aqmLocalBaseAddress;
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if (!cfgInitialized)
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{
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return IX_FAIL;
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}
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if (!IX_QMGR_QID_IS_VALID(qId))
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{
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return IX_QMGR_INVALID_Q_ID;
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}
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else if (NULL == qName)
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN)
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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else if (!qSizeInWordsIsOk (qSizeInWords))
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{
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return IX_QMGR_INVALID_QSIZE;
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}
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else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords))
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{
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return IX_QMGR_INVALID_Q_ENTRY_SIZE;
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}
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else if (cfgQueueInfo[qId].isConfigured)
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{
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return IX_QMGR_Q_ALREADY_CONFIGURED;
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}
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ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER);
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/* Write the config register */
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ixQMgrAqmIfQueCfgWrite (qId,
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qSizeInWords,
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qEntrySizeInWords,
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freeSramAddress);
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strcpy (cfgQueueInfo[qId].qName, qName);
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cfgQueueInfo[qId].qSizeInWords = qSizeInWords;
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cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
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/* store pre-computed information in the same cache line
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* to facilitate inlining of QRead and QWrite functions
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* in IxQMgr.h
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*/
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ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0;
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ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0;
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ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
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ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries =
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(UINT32)qSizeInWords / (UINT32)qEntrySizeInWords;
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/* Calculate the new freeSramAddress from the size of the queue
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* currently being configured.
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*/
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freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD);
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/* Get the virtual SRAM address */
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ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
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IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <=
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IX_QMGR_QUE_BUFFER_SPACE_SIZE);
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/* The queue is now configured */
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cfgQueueInfo[qId].isConfigured = TRUE;
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ixOsalMutexUnlock(&ixQMgrQCfgMutex);
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#ifndef NDEBUG
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/* Update statistics */
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stats.qStats[qId].isConfigured = TRUE;
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stats.qStats[qId].qName = cfgQueueInfo[qId].qName;
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#endif
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return IX_SUCCESS;
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}
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IxQMgrQSizeInWords
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ixQMgrQSizeInWordsGet (IxQMgrQId qId)
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{
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/* No parameter checking as this is used on the data path */
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return (cfgQueueInfo[qId].qSizeInWords);
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}
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IX_STATUS
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ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
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unsigned *qSizeInEntries)
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{
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if (!ixQMgrQIsConfigured(qId))
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{
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return IX_QMGR_Q_NOT_CONFIGURED;
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}
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if(NULL == qSizeInEntries)
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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*qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) /
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(UINT32)cfgQueueInfo[qId].qEntrySizeInWords;
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return IX_SUCCESS;
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}
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IxQMgrQEntrySizeInWords
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ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId)
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{
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/* No parameter checking as this is used on the data path */
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return (cfgQueueInfo[qId].qEntrySizeInWords);
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}
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IX_STATUS
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ixQMgrWatermarkSet (IxQMgrQId qId,
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IxQMgrWMLevel ne,
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IxQMgrWMLevel nf)
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{
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IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
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IxQMgrQStatus qStatusOnExit; /* to this function */
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if (!ixQMgrQIsConfigured(qId))
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{
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return IX_QMGR_Q_NOT_CONFIGURED;
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}
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if (!watermarkLevelIsOk (qId, ne))
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{
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return IX_QMGR_INVALID_Q_WM;
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}
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if (!watermarkLevelIsOk (qId, nf))
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{
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return IX_QMGR_INVALID_Q_WM;
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}
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/* Get the current queue status */
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ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
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#ifndef NDEBUG
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/* Update statistics */
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stats.wmSetCnt++;
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#endif
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ixQMgrAqmIfWatermarkSet (qId,
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ne,
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nf);
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/* Get the current queue status */
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ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
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/* If the status has changed return a warning */
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if (qStatusOnEntry != qStatusOnExit)
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{
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return IX_QMGR_WARNING;
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}
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return IX_SUCCESS;
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}
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IX_STATUS
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ixQMgrAvailableSramAddressGet (UINT32 *address,
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unsigned *sizeOfFreeRam)
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{
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UINT32 aqmLocalBaseAddress;
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if ((NULL == address)||(NULL == sizeOfFreeRam))
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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if (!cfgInitialized)
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{
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return IX_FAIL;
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}
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*address = freeSramAddress;
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/* Get the virtual SRAM address */
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ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
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/*
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* Calculate the size in bytes of free sram
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* i.e. current free SRAM virtual pointer from
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* (base + total size)
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*/
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*sizeOfFreeRam =
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(aqmLocalBaseAddress +
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IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) -
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freeSramAddress;
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if (0 == *sizeOfFreeRam)
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{
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return IX_QMGR_NO_AVAILABLE_SRAM;
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}
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return IX_SUCCESS;
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}
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BOOL
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ixQMgrQIsConfigured (IxQMgrQId qId)
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{
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if (!IX_QMGR_QID_IS_VALID(qId))
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{
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return FALSE;
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}
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return cfgQueueInfo[qId].isConfigured;
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}
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IxQMgrQCfgStats*
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ixQMgrQCfgStatsGet (void)
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{
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return &stats;
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}
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IxQMgrQCfgStats*
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ixQMgrQCfgQStatsGet (IxQMgrQId qId)
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{
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unsigned int ne;
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unsigned int nf;
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UINT32 baseAddress;
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UINT32 readPtr;
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UINT32 writePtr;
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stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords;
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stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords;
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if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
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{
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if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
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{
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IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId);
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}
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}
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ixQMgrAqmIfQueCfgRead (qId,
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stats.qStats[qId].numEntries,
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&baseAddress,
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&ne,
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&nf,
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&readPtr,
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&writePtr);
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stats.qStats[qId].baseAddress = baseAddress;
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stats.qStats[qId].ne = ne;
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stats.qStats[qId].nf = nf;
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stats.qStats[qId].readPtr = readPtr;
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stats.qStats[qId].writePtr = writePtr;
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return &stats;
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}
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/*
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* Static function definitions
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*/
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PRIVATE BOOL
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watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level)
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{
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unsigned qSizeInEntries;
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switch (level)
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{
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case IX_QMGR_Q_WM_LEVEL0:
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case IX_QMGR_Q_WM_LEVEL1:
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case IX_QMGR_Q_WM_LEVEL2:
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case IX_QMGR_Q_WM_LEVEL4:
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case IX_QMGR_Q_WM_LEVEL8:
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case IX_QMGR_Q_WM_LEVEL16:
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case IX_QMGR_Q_WM_LEVEL32:
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case IX_QMGR_Q_WM_LEVEL64:
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break;
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default:
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return FALSE;
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}
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/* Check watermark is not bigger than the qSizeInEntries */
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ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries);
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if ((unsigned)level > qSizeInEntries)
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{
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return FALSE;
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}
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return TRUE;
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}
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PRIVATE BOOL
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qSizeInWordsIsOk (IxQMgrQSizeInWords qSize)
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{
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BOOL status;
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switch (qSize)
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{
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case IX_QMGR_Q_SIZE16:
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case IX_QMGR_Q_SIZE32:
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case IX_QMGR_Q_SIZE64:
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case IX_QMGR_Q_SIZE128:
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status = TRUE;
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break;
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default:
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status = FALSE;
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break;
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}
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return status;
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}
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PRIVATE BOOL
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qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize)
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{
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BOOL status;
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switch (entrySize)
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{
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case IX_QMGR_Q_ENTRY_SIZE1:
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case IX_QMGR_Q_ENTRY_SIZE2:
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case IX_QMGR_Q_ENTRY_SIZE4:
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status = TRUE;
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break;
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default:
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status = FALSE;
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break;
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}
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return status;
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}
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