mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 19:43:33 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
200 lines
4.7 KiB
Text
200 lines
4.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2013 Altera Corporation
|
|
*
|
|
* This file is generated by sopc2dts.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
model = "altr,qsys_ghrd_3c120";
|
|
compatible = "altr,qsys_ghrd_3c120";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu: cpu@0x0 {
|
|
device_type = "cpu";
|
|
compatible = "altr,nios2-1.0";
|
|
reg = <0x00000000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
clock-frequency = <125000000>;
|
|
dcache-line-size = <32>;
|
|
icache-line-size = <32>;
|
|
dcache-size = <32768>;
|
|
icache-size = <32768>;
|
|
altr,implementation = "fast";
|
|
altr,pid-num-bits = <8>;
|
|
altr,tlb-num-ways = <16>;
|
|
altr,tlb-num-entries = <128>;
|
|
altr,tlb-ptr-sz = <7>;
|
|
altr,has-div = <1>;
|
|
altr,has-mul = <1>;
|
|
altr,reset-addr = <0xc2800000>;
|
|
altr,fast-tlb-miss-addr = <0xc7fff400>;
|
|
altr,exception-addr = <0xd0000020>;
|
|
altr,has-initda = <1>;
|
|
altr,has-mmu = <1>;
|
|
};
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x10000000 0x08000000>,
|
|
<0x07fff400 0x00000400>;
|
|
};
|
|
|
|
sopc@0 {
|
|
device_type = "soc";
|
|
ranges;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "altr,avalon", "simple-bus";
|
|
bus-frequency = <125000000>;
|
|
|
|
pb_cpu_to_io: bridge@0x8000000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x08000000 0x00800000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00002000 0x08002000 0x00002000>,
|
|
<0x00004000 0x08004000 0x00000400>,
|
|
<0x00004400 0x08004400 0x00000040>,
|
|
<0x00004800 0x08004800 0x00000040>,
|
|
<0x00004c80 0x08004c80 0x00000020>,
|
|
<0x00004cc0 0x08004cc0 0x00000010>,
|
|
<0x00004ce0 0x08004ce0 0x00000010>,
|
|
<0x00004d00 0x08004d00 0x00000010>,
|
|
<0x00004d40 0x08004d40 0x00000008>,
|
|
<0x00004d50 0x08004d50 0x00000008>,
|
|
<0x00008000 0x08008000 0x00000020>,
|
|
<0x00400000 0x08400000 0x00000020>;
|
|
|
|
timer_1ms: timer@0x400000 {
|
|
compatible = "altr,timer-1.0";
|
|
reg = <0x00400000 0x00000020>;
|
|
interrupt-parent = <&cpu>;
|
|
interrupts = <11>;
|
|
clock-frequency = <125000000>;
|
|
};
|
|
|
|
timer_0: timer@0x8000 {
|
|
compatible = "altr,timer-1.0";
|
|
reg = < 0x00008000 0x00000020 >;
|
|
interrupt-parent = < &cpu >;
|
|
interrupts = < 5 >;
|
|
clock-frequency = < 125000000 >;
|
|
};
|
|
|
|
sysid: sysid@0x4d40 {
|
|
compatible = "altr,sysid-1.0";
|
|
reg = <0x00004d40 0x00000008>;
|
|
};
|
|
|
|
jtag_uart: serial@0x4d50 {
|
|
compatible = "altr,juart-1.0";
|
|
reg = <0x00004d50 0x00000008>;
|
|
interrupt-parent = <&cpu>;
|
|
interrupts = <1>;
|
|
};
|
|
|
|
tse_mac: ethernet@0x4000 {
|
|
compatible = "altr,tse-1.0";
|
|
reg = <0x00004000 0x00000400>,
|
|
<0x00004400 0x00000040>,
|
|
<0x00004800 0x00000040>,
|
|
<0x00002000 0x00002000>;
|
|
reg-names = "control_port", "rx_csr", "tx_csr", "s1";
|
|
interrupt-parent = <&cpu>;
|
|
interrupts = <2 3>;
|
|
interrupt-names = "rx_irq", "tx_irq";
|
|
rx-fifo-depth = <8192>;
|
|
tx-fifo-depth = <8192>;
|
|
max-frame-size = <1518>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <&phy0>;
|
|
tse_mac_mdio: mdio {
|
|
compatible = "altr,tse-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
phy0: ethernet-phy@18 {
|
|
reg = <18>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
};
|
|
};
|
|
|
|
uart: serial@0x4c80 {
|
|
compatible = "altr,uart-1.0";
|
|
reg = <0x00004c80 0x00000020>;
|
|
interrupt-parent = <&cpu>;
|
|
interrupts = <10>;
|
|
current-speed = <115200>;
|
|
clock-frequency = <62500000>;
|
|
};
|
|
|
|
user_led_pio_8out: gpio@0x4cc0 {
|
|
compatible = "altr,pio-1.0";
|
|
reg = <0x00004cc0 0x00000010>;
|
|
resetvalue = <255>;
|
|
altr,gpio-bank-width = <8>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-bank-name = "led";
|
|
};
|
|
|
|
user_dipsw_pio_8in: gpio@0x4ce0 {
|
|
compatible = "altr,pio-1.0";
|
|
reg = <0x00004ce0 0x00000010>;
|
|
interrupt-parent = <&cpu>;
|
|
interrupts = <8>;
|
|
edge_type = <2>;
|
|
level_trigger = <0>;
|
|
resetvalue = <0>;
|
|
altr,gpio-bank-width = <8>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-bank-name = "dipsw";
|
|
};
|
|
|
|
user_pb_pio_4in: gpio@0x4d00 {
|
|
compatible = "altr,pio-1.0";
|
|
reg = <0x00004d00 0x00000010>;
|
|
interrupt-parent = <&cpu>;
|
|
interrupts = <9>;
|
|
edge_type = <2>;
|
|
level_trigger = <0>;
|
|
resetvalue = <0>;
|
|
altr,gpio-bank-width = <4>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-bank-name = "pb";
|
|
};
|
|
};
|
|
|
|
cfi_flash_64m: flash@0x0 {
|
|
compatible = "cfi-flash";
|
|
reg = <0x00000000 0x04000000>;
|
|
bank-width = <2>;
|
|
device-width = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@800000 {
|
|
reg = <0x00800000 0x01e00000>;
|
|
label = "JFFS2 Filesystem";
|
|
};
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "debug console=ttyJ0,115200";
|
|
stdout-path = &jtag_uart;
|
|
};
|
|
};
|