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1d71bbca45
Implement write support for Security OTP values via mailbox API commands MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE. Write support for North and South Bridge OTPs are not implemented as these OTPs are already burned in factory with some data. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz>
217 lines
5.5 KiB
C
217 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) 2017 Marvell International Ltd.
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* (C) 2021 Pali Rohár <pali@kernel.org>
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <mach/mbox.h>
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#include <mach/soc.h>
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#define OTP_NB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x12600))
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#define OTP_SB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x1A200))
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#define OTP_CONTROL_OFF 0x00
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#define OTP_MODE_BIT BIT(15)
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#define OTP_RPTR_RST_BIT BIT(14)
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#define OTP_POR_B_BIT BIT(13)
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#define OTP_PRDT_BIT BIT(3)
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#define OTP_READ_PORT_OFF 0x04
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#define OTP_READ_POINTER_OFF 0x08
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#define OTP_PTR_INC_BIT BIT(8)
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static void otp_read_parallel(void __iomem *base, u32 *data, u32 count)
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{
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u32 regval;
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/* 1. Clear OTP_MODE_NB to parallel mode */
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regval = readl(base + OTP_CONTROL_OFF);
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regval &= ~OTP_MODE_BIT;
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writel(regval, base + OTP_CONTROL_OFF);
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/* 2. Set OTP_POR_B_NB enter normal operation */
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regval = readl(base + OTP_CONTROL_OFF);
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regval |= OTP_POR_B_BIT;
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writel(regval, base + OTP_CONTROL_OFF);
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/* 3. Set OTP_PTR_INC_NB to auto-increment pointer after each read */
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regval = readl(base + OTP_READ_POINTER_OFF);
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regval |= OTP_PTR_INC_BIT;
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writel(regval, base + OTP_READ_POINTER_OFF);
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/* 4. Set OTP_RPTR_RST_NB, then clear the same field */
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regval = readl(base + OTP_CONTROL_OFF);
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regval |= OTP_RPTR_RST_BIT;
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writel(regval, base + OTP_CONTROL_OFF);
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regval = readl(base + OTP_CONTROL_OFF);
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regval &= ~OTP_RPTR_RST_BIT;
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writel(regval, base + OTP_CONTROL_OFF);
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/* 5. Toggle OTP_PRDT_NB
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* a. Set OTP_PRDT_NB to 1.
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* b. Clear OTP_PRDT_NB to 0.
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* c. Wait for a minimum of 100 ns.
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* d. Set OTP_PRDT_NB to 1
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*/
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regval = readl(base + OTP_CONTROL_OFF);
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regval |= OTP_PRDT_BIT;
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writel(regval, base + OTP_CONTROL_OFF);
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regval = readl(base + OTP_CONTROL_OFF);
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regval &= ~OTP_PRDT_BIT;
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writel(regval, base + OTP_CONTROL_OFF);
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ndelay(100);
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regval = readl(base + OTP_CONTROL_OFF);
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regval |= OTP_PRDT_BIT;
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writel(regval, base + OTP_CONTROL_OFF);
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while (count-- > 0) {
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/* 6. Read the content of OTP 32-bits at a time */
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ndelay(100000);
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*(data++) = readl(base + OTP_READ_PORT_OFF);
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}
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}
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static int rwtm_otp_read(u8 row, u32 word, u32 *data)
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{
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u32 out[3];
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u32 in[2];
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int res = -EINVAL;
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if (word < 2) {
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/*
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* MBOX_CMD_OTP_READ_32B command is supported by Marvell
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* fuse.bin firmware and also by new CZ.NIC wtmi firmware.
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* This command returns raw bits without ECC corrections.
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* It does not provide access to the lock bit.
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*/
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in[0] = row;
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in[1] = word * 32;
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res = mbox_do_cmd(MBOX_CMD_OTP_READ_32B, in, 2, out, 1);
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if (!res)
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*data = out[0];
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} else if (word == 2) {
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/*
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* MBOX_CMD_OTP_READ command is supported only by new CZ.NIC
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* wtmi firmware and provides access to all bits, including
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* lock bit without doing ECC corrections. For compatibility
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* with Marvell fuse.bin firmware, use this command only for
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* accessing lock bit.
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*/
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in[0] = row;
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res = mbox_do_cmd(MBOX_CMD_OTP_READ, in, 1, out, 3);
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if (!res)
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*data = out[2];
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}
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return res;
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}
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static int rwtm_otp_write(u8 row, u32 word, u32 data)
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{
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u32 in[4];
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int res = -EINVAL;
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if (word < 2) {
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/*
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* MBOX_CMD_OTP_WRITE_32B command is supported by Marvell
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* fuse.bin firmware and also by new CZ.NIC wtmi firmware.
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* This command writes only selected bits to OTP and does
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* not calculate ECC bits. It does not allow to write the
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* lock bit.
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*/
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in[0] = row;
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in[1] = word * 32;
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in[2] = data;
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res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0);
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} else if (word == 2 && !(data & ~0x1)) {
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/*
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* MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC
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* wtmi firmware and allows to write any bit to OTP, including
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* the lock bit. It does not calculate or write ECC bits too.
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* For compatibility with Marvell fuse.bin firmware, use this
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* command only for writing the lock bit.
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*/
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in[0] = row;
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in[1] = 0;
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in[2] = 0;
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in[3] = data;
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res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0);
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}
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return res;
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}
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/*
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* Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2)
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* Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2)
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* Bank 45 is used for accessing South Bridge OTP (97 bits via words 0-3)
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*/
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#define RWTM_ROWS 44
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#define RWTM_MAX_BANK (RWTM_ROWS - 1)
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#define RWTM_ROW_WORDS 3
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#define OTP_NB_BANK RWTM_ROWS
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#define OTP_NB_WORDS 3
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#define OTP_SB_BANK (RWTM_ROWS + 1)
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#define OTP_SB_WORDS 4
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int fuse_read(u32 bank, u32 word, u32 *val)
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{
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if (bank <= RWTM_MAX_BANK) {
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if (word >= RWTM_ROW_WORDS)
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return -EINVAL;
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return rwtm_otp_read(bank, word, val);
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} else if (bank == OTP_NB_BANK) {
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u32 data[OTP_NB_WORDS];
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if (word >= OTP_NB_WORDS)
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return -EINVAL;
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otp_read_parallel(OTP_NB_REG_BASE, data, OTP_NB_WORDS);
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*val = data[word];
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return 0;
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} else if (bank == OTP_SB_BANK) {
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u32 data[OTP_SB_WORDS];
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if (word >= OTP_SB_WORDS)
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return -EINVAL;
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otp_read_parallel(OTP_SB_REG_BASE, data, OTP_SB_WORDS);
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*val = data[word];
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return 0;
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} else {
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return -EINVAL;
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}
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}
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int fuse_prog(u32 bank, u32 word, u32 val)
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{
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if (bank <= RWTM_MAX_BANK) {
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if (word >= RWTM_ROW_WORDS)
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return -EINVAL;
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return rwtm_otp_write(bank, word, val);
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} else if (bank == OTP_NB_BANK) {
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/* TODO: not implemented yet */
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return -ENOSYS;
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} else if (bank == OTP_SB_BANK) {
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/* TODO: not implemented yet */
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return -ENOSYS;
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} else {
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return -EINVAL;
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}
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}
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int fuse_sense(u32 bank, u32 word, u32 *val)
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{
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/* not supported */
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return -ENOSYS;
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}
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int fuse_override(u32 bank, u32 word, u32 val)
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{
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/* not supported */
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return -ENOSYS;
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}
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