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4ae8bc4392
This patch adds SPL support for SPEAr600. Currently only SNOR (Serial NOR) flash support is included. Other boot devices (NAND, MMC, USB ...) may be added with later patches. Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
273 lines
7.9 KiB
C
273 lines
7.9 KiB
C
/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SPR_MISC_H
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#define _SPR_MISC_H
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struct misc_regs {
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u32 auto_cfg_reg; /* 0x0 */
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u32 armdbg_ctr_reg; /* 0x4 */
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u32 pll1_cntl; /* 0x8 */
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u32 pll1_frq; /* 0xc */
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u32 pll1_mod; /* 0x10 */
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u32 pll2_cntl; /* 0x14 */
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u32 pll2_frq; /* 0x18 */
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u32 pll2_mod; /* 0x1C */
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u32 pll_ctr_reg; /* 0x20 */
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u32 amba_clk_cfg; /* 0x24 */
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u32 periph_clk_cfg; /* 0x28 */
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u32 periph1_clken; /* 0x2C */
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u32 soc_core_id; /* 0x30 */
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u32 ras_clken; /* 0x34 */
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u32 periph1_rst; /* 0x38 */
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u32 periph2_rst; /* 0x3C */
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u32 ras_rst; /* 0x40 */
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u32 prsc1_clk_cfg; /* 0x44 */
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u32 prsc2_clk_cfg; /* 0x48 */
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u32 prsc3_clk_cfg; /* 0x4C */
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u32 amem_cfg_ctrl; /* 0x50 */
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u32 expi_clk_cfg; /* 0x54 */
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u32 reserved_1; /* 0x58 */
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u32 clcd_synth_clk; /* 0x5C */
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u32 irda_synth_clk; /* 0x60 */
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u32 uart_synth_clk; /* 0x64 */
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u32 gmac_synth_clk; /* 0x68 */
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u32 ras_synth1_clk; /* 0x6C */
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u32 ras_synth2_clk; /* 0x70 */
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u32 ras_synth3_clk; /* 0x74 */
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u32 ras_synth4_clk; /* 0x78 */
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u32 arb_icm_ml1; /* 0x7C */
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u32 arb_icm_ml2; /* 0x80 */
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u32 arb_icm_ml3; /* 0x84 */
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u32 arb_icm_ml4; /* 0x88 */
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u32 arb_icm_ml5; /* 0x8C */
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u32 arb_icm_ml6; /* 0x90 */
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u32 arb_icm_ml7; /* 0x94 */
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u32 arb_icm_ml8; /* 0x98 */
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u32 arb_icm_ml9; /* 0x9C */
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u32 dma_src_sel; /* 0xA0 */
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u32 uphy_ctr_reg; /* 0xA4 */
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u32 gmac_ctr_reg; /* 0xA8 */
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u32 port_bridge_ctrl; /* 0xAC */
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u32 reserved_2[4]; /* 0xB0--0xBC */
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u32 prc1_ilck_ctrl_reg; /* 0xC0 */
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u32 prc2_ilck_ctrl_reg; /* 0xC4 */
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u32 prc3_ilck_ctrl_reg; /* 0xC8 */
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u32 prc4_ilck_ctrl_reg; /* 0xCC */
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u32 prc1_intr_ctrl_reg; /* 0xD0 */
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u32 prc2_intr_ctrl_reg; /* 0xD4 */
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u32 prc3_intr_ctrl_reg; /* 0xD8 */
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u32 prc4_intr_ctrl_reg; /* 0xDC */
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u32 powerdown_cfg_reg; /* 0xE0 */
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u32 ddr_1v8_compensation; /* 0xE4 */
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u32 ddr_2v5_compensation; /* 0xE8 */
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u32 core_3v3_compensation; /* 0xEC */
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u32 ddr_pad; /* 0xF0 */
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u32 bist1_ctr_reg; /* 0xF4 */
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u32 bist2_ctr_reg; /* 0xF8 */
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u32 bist3_ctr_reg; /* 0xFC */
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u32 bist4_ctr_reg; /* 0x100 */
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u32 bist5_ctr_reg; /* 0x104 */
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u32 bist1_rslt_reg; /* 0x108 */
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u32 bist2_rslt_reg; /* 0x10C */
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u32 bist3_rslt_reg; /* 0x110 */
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u32 bist4_rslt_reg; /* 0x114 */
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u32 bist5_rslt_reg; /* 0x118 */
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u32 syst_error_reg; /* 0x11C */
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u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */
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u32 ras_gpp1_in; /* 0x8000 */
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u32 ras_gpp2_in; /* 0x8004 */
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u32 ras_gpp1_out; /* 0x8008 */
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u32 ras_gpp2_out; /* 0x800C */
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};
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/* SYNTH_CLK value*/
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#define SYNTH23 0x00020003
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/* PLLx_FRQ value */
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#if defined(CONFIG_SPEAR3XX)
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#define FREQ_332 0xA600010C
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#define FREQ_266 0x8500010C
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#elif defined(CONFIG_SPEAR600)
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#define FREQ_332 0xA600010F
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#define FREQ_266 0x8500010F
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#endif
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/* PLL_CTR_REG */
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#define MEM_CLK_SEL_MSK 0x70000000
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#define MEM_CLK_HCLK 0x00000000
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#define MEM_CLK_2HCLK 0x10000000
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#define MEM_CLK_PLL2 0x30000000
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#define EXPI_CLK_CFG_LOW_COMPR 0x2000
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#define EXPI_CLK_CFG_CLK_EN 0x0400
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#define EXPI_CLK_CFG_RST 0x0200
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#define EXPI_CLK_SYNT_EN 0x0010
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#define EXPI_CLK_CFG_SEL_PLL2 0x0004
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#define EXPI_CLK_CFG_INT_CLK_EN 0x0001
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#define PLL2_CNTL_6UA 0x1c00
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#define PLL2_CNTL_SAMPLE 0x0008
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#define PLL2_CNTL_ENABLE 0x0004
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#define PLL2_CNTL_RESETN 0x0002
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#define PLL2_CNTL_LOCK 0x0001
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/* AUTO_CFG_REG value */
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#define MISC_SOCCFGMSK 0x0000003F
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#define MISC_SOCCFG30 0x0000000C
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#define MISC_SOCCFG31 0x0000000D
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#define MISC_NANDDIS 0x00020000
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/* PERIPH_CLK_CFG value */
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#define MISC_GPT3SYNTH 0x00000400
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#define MISC_GPT4SYNTH 0x00000800
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#define CONFIG_SPEAR_UART48M 0
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#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
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/* PRSC_CLK_CFG value */
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/*
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* Fout = Fin / (2^(N+1) * (M + 1))
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*/
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#define MISC_PRSC_N_1 0x00001000
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#define MISC_PRSC_M_9 0x00000009
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#define MISC_PRSC_N_4 0x00004000
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#define MISC_PRSC_M_399 0x0000018F
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#define MISC_PRSC_N_6 0x00006000
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#define MISC_PRSC_M_2593 0x00000A21
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#define MISC_PRSC_M_124 0x0000007C
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#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9)
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/* PERIPH1_CLKEN, PERIPH1_RST value */
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#define MISC_USBDENB 0x01000000
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#define MISC_ETHENB 0x00800000
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#define MISC_SMIENB 0x00200000
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#define MISC_GPT3ENB 0x00010000
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#define MISC_GPIO4ENB 0x00002000
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#define MISC_GPT2ENB 0x00000800
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#define MISC_FSMCENB 0x00000200
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#define MISC_I2CENB 0x00000080
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#define MISC_SSP2ENB 0x00000070
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#define MISC_UART0ENB 0x00000008
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/* PERIPH_CLK_CFG */
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#define XTALTIMEEN 0x00000001
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#define PLLTIMEEN 0x00000002
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#define CLCDCLK_SYNTH 0x00000000
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#define CLCDCLK_48MHZ 0x00000004
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#define CLCDCLK_EXT 0x00000008
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#define UARTCLK_MASK (0x1 << 4)
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#define UARTCLK_48MHZ 0x00000000
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#define UARTCLK_SYNTH 0x00000010
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#define IRDACLK_48MHZ 0x00000000
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#define IRDACLK_SYNTH 0x00000020
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#define IRDACLK_EXT 0x00000040
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#define RTC_DISABLE 0x00000080
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#define GPT1CLK_48MHZ 0x00000000
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#define GPT1CLK_SYNTH 0x00000100
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#define GPT2CLK_48MHZ 0x00000000
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#define GPT2CLK_SYNTH 0x00000200
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#define GPT3CLK_48MHZ 0x00000000
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#define GPT3CLK_SYNTH 0x00000400
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#define GPT4CLK_48MHZ 0x00000000
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#define GPT4CLK_SYNTH 0x00000800
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#define GPT5CLK_48MHZ 0x00000000
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#define GPT5CLK_SYNTH 0x00001000
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#define GPT1_FREEZE 0x00002000
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#define GPT2_FREEZE 0x00004000
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#define GPT3_FREEZE 0x00008000
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#define GPT4_FREEZE 0x00010000
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#define GPT5_FREEZE 0x00020000
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/* PERIPH1_CLKEN bits */
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#define PERIPH_ARM1_WE 0x00000001
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#define PERIPH_ARM1 0x00000002
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#define PERIPH_ARM2 0x00000004
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#define PERIPH_UART1 0x00000008
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#define PERIPH_UART2 0x00000010
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#define PERIPH_SSP1 0x00000020
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#define PERIPH_SSP2 0x00000040
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#define PERIPH_I2C 0x00000080
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#define PERIPH_JPEG 0x00000100
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#define PERIPH_FSMC 0x00000200
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#define PERIPH_FIRDA 0x00000400
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#define PERIPH_GPT4 0x00000800
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#define PERIPH_GPT5 0x00001000
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#define PERIPH_GPIO4 0x00002000
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#define PERIPH_SSP3 0x00004000
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#define PERIPH_ADC 0x00008000
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#define PERIPH_GPT3 0x00010000
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#define PERIPH_RTC 0x00020000
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#define PERIPH_GPIO3 0x00040000
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#define PERIPH_DMA 0x00080000
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#define PERIPH_ROM 0x00100000
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#define PERIPH_SMI 0x00200000
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#define PERIPH_CLCD 0x00400000
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#define PERIPH_GMAC 0x00800000
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#define PERIPH_USBD 0x01000000
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#define PERIPH_USBH1 0x02000000
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#define PERIPH_USBH2 0x04000000
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#define PERIPH_MPMC 0x08000000
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#define PERIPH_RAMW 0x10000000
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#define PERIPH_MPMC_EN 0x20000000
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#define PERIPH_MPMC_WE 0x40000000
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#define PERIPH_MPMCMSK 0x60000000
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#define PERIPH_CLK_ALL 0x0FFFFFF8
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#define PERIPH_RST_ALL 0x00000004
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/* DDR_PAD values */
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#define DDR_PAD_CNF_MSK 0x0000ffff
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#define DDR_PAD_SW_CONF 0x00060000
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#define DDR_PAD_SSTL_SEL 0x00000001
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#define DDR_PAD_DRAM_TYPE 0x00008000
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/* DDR_COMP values */
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#define DDR_COMP_ACCURATE 0x00000010
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/* SoC revision stuff */
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#define SOC_PRI_SHFT 16
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#define SOC_SEC_SHFT 8
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/* Revision definitions */
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#define SOC_SPEAR_NA 0
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/*
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* The definitons have started from
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* 101 for SPEAr6xx
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* 201 for SPEAr3xx
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* 301 for SPEAr13xx
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*/
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#define SOC_SPEAR600_AA 101
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#define SOC_SPEAR600_AB 102
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#define SOC_SPEAR600_BA 103
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#define SOC_SPEAR600_BB 104
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#define SOC_SPEAR600_BC 105
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#define SOC_SPEAR600_BD 106
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#define SOC_SPEAR300 201
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#define SOC_SPEAR310 202
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#define SOC_SPEAR320 203
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extern int get_socrev(void);
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#endif
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