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https://github.com/AsahiLinux/u-boot
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e160f7d430
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
278 lines
6.9 KiB
C
278 lines
6.9 KiB
C
/*
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* Copyright (C) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <pch.h>
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#include <pci.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/gpio.h>
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#include <dt-bindings/gpio/x86-gpio.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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MAX_GPIOS = 95,
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};
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#define PIRQ_SHIFT 16
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#define CONF_MASK 0xffff
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struct pin_info {
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int node;
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int phandle;
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bool mode_gpio;
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bool dir_input;
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bool invert;
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bool trigger_level;
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bool output_high;
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bool sense_disable;
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bool owner_gpio;
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bool route_smi;
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bool irq_enable;
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bool reset_rsmrst;
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bool pirq_apic_route;
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};
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static int broadwell_pinctrl_read_configs(struct udevice *dev,
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struct pin_info *conf, int max_pins)
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{
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const void *blob = gd->fdt_blob;
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int count = 0;
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int node;
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debug("%s: starting\n", __func__);
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for (node = fdt_first_subnode(blob, dev_of_offset(dev));
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node > 0;
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node = fdt_next_subnode(blob, node)) {
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int phandle = fdt_get_phandle(blob, node);
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if (!phandle)
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continue;
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if (count == max_pins)
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return -ENOSPC;
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/* We've found a new configuration */
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memset(conf, '\0', sizeof(*conf));
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conf->node = node;
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conf->phandle = phandle;
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conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio");
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if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT)
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conf->dir_input = true;
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conf->invert = fdtdec_get_bool(blob, node, "invert");
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if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL)
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conf->trigger_level = true;
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if (fdtdec_get_int(blob, node, "output-value", -1) == 1)
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conf->output_high = true;
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conf->sense_disable = fdtdec_get_bool(blob, node,
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"sense-disable");
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if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO)
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conf->owner_gpio = true;
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if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI)
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conf->route_smi = true;
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conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable");
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conf->reset_rsmrst = fdtdec_get_bool(blob, node,
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"reset-rsmrst");
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if (fdtdec_get_int(blob, node, "pirq-apic", -1) ==
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PIRQ_APIC_ROUTE)
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conf->pirq_apic_route = true;
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debug("config: phandle=%d\n", phandle);
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count++;
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conf++;
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}
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debug("%s: Found %d configurations\n", __func__, count);
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return count;
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}
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static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf,
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int conf_count, int phandle)
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{
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int i;
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for (i = 0; i < conf_count; i++) {
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if (conf[i].phandle == phandle)
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return i;
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}
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return -ENOENT;
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}
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static int broadwell_pinctrl_read_pins(struct udevice *dev,
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struct pin_info *conf, int conf_count, int gpio_conf[],
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int num_gpios)
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{
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const void *blob = gd->fdt_blob;
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int count = 0;
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int node;
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for (node = fdt_first_subnode(blob, dev_of_offset(dev));
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node > 0;
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node = fdt_next_subnode(blob, node)) {
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int len, i;
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const u32 *prop = fdt_getprop(blob, node, "config", &len);
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if (!prop)
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continue;
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/* There are three cells per pin */
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count = len / (sizeof(u32) * 3);
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debug("Found %d GPIOs to configure\n", count);
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for (i = 0; i < count; i++) {
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uint gpio = fdt32_to_cpu(prop[i * 3]);
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uint phandle = fdt32_to_cpu(prop[i * 3 + 1]);
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int val;
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if (gpio >= num_gpios) {
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debug("%s: GPIO %d out of range\n", __func__,
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gpio);
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return -EDOM;
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}
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val = broadwell_pinctrl_lookup_phandle(conf, conf_count,
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phandle);
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if (val < 0) {
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debug("%s: Cannot find phandle %d\n", __func__,
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phandle);
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return -EINVAL;
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}
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gpio_conf[gpio] = val |
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fdt32_to_cpu(prop[i * 3 + 2]) << PIRQ_SHIFT;
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}
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}
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return 0;
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}
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static void broadwell_pinctrl_commit(struct pch_lp_gpio_regs *regs,
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struct pin_info *pin_info,
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int gpio_conf[], int count)
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{
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u32 owner_gpio[GPIO_BANKS] = {0};
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u32 route_smi[GPIO_BANKS] = {0};
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u32 irq_enable[GPIO_BANKS] = {0};
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u32 reset_rsmrst[GPIO_BANKS] = {0};
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u32 pirq2apic = 0;
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int set, bit, gpio = 0;
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for (gpio = 0; gpio < MAX_GPIOS; gpio++) {
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int confnum = gpio_conf[gpio] & CONF_MASK;
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struct pin_info *pin = &pin_info[confnum];
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u32 val;
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val = pin->mode_gpio << CONFA_MODE_SHIFT |
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pin->dir_input << CONFA_DIR_SHIFT |
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pin->invert << CONFA_INVERT_SHIFT |
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pin->trigger_level << CONFA_TRIGGER_SHIFT |
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pin->output_high << CONFA_OUTPUT_SHIFT;
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outl(val, ®s->config[gpio].conf_a);
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outl(pin->sense_disable << CONFB_SENSE_SHIFT,
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®s->config[gpio].conf_b);
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/* Determine set and bit based on GPIO number */
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set = gpio / GPIO_PER_BANK;
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bit = gpio % GPIO_PER_BANK;
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/* Apply settings to set specific bits */
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owner_gpio[set] |= pin->owner_gpio << bit;
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route_smi[set] |= pin->route_smi << bit;
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irq_enable[set] |= pin->irq_enable << bit;
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reset_rsmrst[set] |= pin->reset_rsmrst << bit;
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/* PIRQ to IO-APIC map */
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if (pin->pirq_apic_route)
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pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT;
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debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n",
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gpio, confnum, pin->mode_gpio, pin->dir_input,
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pin->output_high);
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}
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for (set = 0; set < GPIO_BANKS; set++) {
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outl(owner_gpio[set], ®s->own[set]);
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outl(route_smi[set], ®s->gpi_route[set]);
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outl(irq_enable[set], ®s->gpi_ie[set]);
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outl(reset_rsmrst[set], ®s->rst_sel[set]);
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}
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outl(pirq2apic, ®s->pirq_to_ioxapic);
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}
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static int broadwell_pinctrl_probe(struct udevice *dev)
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{
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struct pch_lp_gpio_regs *regs;
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struct pin_info conf[12];
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int gpio_conf[MAX_GPIOS];
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struct udevice *pch;
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int conf_count;
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u32 gpiobase;
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int ret;
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ret = uclass_first_device(UCLASS_PCH, &pch);
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if (ret)
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return ret;
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if (!pch)
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return -ENODEV;
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debug("%s: start\n", __func__);
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/* Only init once, before relocation */
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if (gd->flags & GD_FLG_RELOC)
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return 0;
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/*
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* Get the memory/io base address to configure every pins.
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* IOBASE is used to configure the mode/pads
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* GPIOBASE is used to configure the direction and default value
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*/
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ret = pch_get_gpio_base(pch, &gpiobase);
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if (ret) {
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debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
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gpiobase);
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return -EINVAL;
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}
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conf_count = broadwell_pinctrl_read_configs(dev, conf,
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ARRAY_SIZE(conf));
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if (conf_count < 0) {
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debug("%s: Cannot read configs: err=%d\n", __func__, ret);
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return conf_count;
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}
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/*
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* Assume that pin settings are provided for every pin. Pins not
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* mentioned will get the first config mentioned in the list.
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*/
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ret = broadwell_pinctrl_read_pins(dev, conf, conf_count, gpio_conf,
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MAX_GPIOS);
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if (ret) {
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debug("%s: Cannot read pin settings: err=%d\n", __func__, ret);
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return ret;
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}
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regs = (struct pch_lp_gpio_regs *)gpiobase;
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broadwell_pinctrl_commit(regs, conf, gpio_conf, ARRAY_SIZE(conf));
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debug("%s: done\n", __func__);
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return 0;
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}
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static const struct udevice_id broadwell_pinctrl_match[] = {
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{ .compatible = "intel,x86-broadwell-pinctrl",
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.data = X86_SYSCON_PINCONF },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(broadwell_pinctrl) = {
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.name = "broadwell_pinctrl",
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.id = UCLASS_SYSCON,
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.of_match = broadwell_pinctrl_match,
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.probe = broadwell_pinctrl_probe,
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};
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