mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 09:30:10 +00:00
4e5114daf9
Synchronise device tree with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
170 lines
4.3 KiB
Text
170 lines
4.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 Collabora Ltd.
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* Copyright 2021 BSH Hausgeraete GmbH
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*/
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/dts-v1/;
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#include "imx8mn-bsh-smm-s2-common.dtsi"
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#include <dt-bindings/sound/tlv320aic31xx.h>
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/ {
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model = "BSH SMM S2 PRO";
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compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0x20000000>;
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};
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sound-tlv320aic31xx {
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compatible = "fsl,imx-audio-tlv320aic31xx";
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model = "tlv320aic31xx-hifi";
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audio-cpu = <&sai3>;
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audio-codec = <&tlv320dac3101>;
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audio-asrc = <&easrc>;
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audio-routing =
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"Ext Spk", "SPL",
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"Ext Spk", "SPR";
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mclk-id = <PLL_CLKIN_BCLK>;
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};
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vdd_input: vdd_input {
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compatible = "regulator-fixed";
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regulator-name = "vdd_input";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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};
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&easrc {
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fsl,asrc-rate = <48000>;
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fsl,asrc-format = <10>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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tlv320dac3101: audio-codec@18 {
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compatible = "ti,tlv320dac3101";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dac_rst>;
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reg = <0x18>;
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#sound-dai-cells = <0>;
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HPVDD-supply = <&buck4_reg>;
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SPRVDD-supply = <&vdd_input>;
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SPLVDD-supply = <&vdd_input>;
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AVDD-supply = <&buck4_reg>;
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IOVDD-supply = <&buck4_reg>;
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DVDD-supply = <&buck5_reg>;
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reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
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ai31xx-micbias-vg = <MICBIAS_AVDDV>;
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clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
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};
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};
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
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assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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/* eMMC */
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl_dac_rst: dacrstgrp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */
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>;
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};
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pinctrl_espi2: espi2grp {
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fsl,pins = <
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MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
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MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
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MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
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MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
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MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
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>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
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MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
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MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0
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MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0
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MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0
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MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0
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MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0
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MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4
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MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4
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MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4
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MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4
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MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4
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MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6
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MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6
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MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6
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MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6
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MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6
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MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096
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>;
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};
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};
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