mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
62be2367f5
The sequence number assigned for USB subsystem in a uclass is dependent on the order of occurrence in the device tree. If the dr_mode of USB3SS0 controller is varied then the sequence number of USB3SS1 controller also changes. If aliases are added then sequence numbers are assigned using the alias number. This makes the sequence number of USB3SS1 controller independent of USB3SS0 controller's dr_mode. Therefore, add aliases to fix the sequence number assigned to the USB subsystems. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
281 lines
6.2 KiB
Text
281 lines
6.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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};
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aliases {
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serial2 = &main_uart0;
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ethernet0 = &cpsw_port1;
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usb0 = &usb0;
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usb1 = &usb1;
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};
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};
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&cbass_main{
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u-boot,dm-spl;
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sdhci1: sdhci@04FA0000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4FA0000 0x0 0x1000>,
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<0x0 0x4FB0000 0x0 0x400>;
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clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
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clock-names = "clk_ahb", "clk_xin";
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power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
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max-frequency = <25000000>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0x0>;
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ti,otap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr50 = <0x8>;
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ti,otap-del-sel-sdr104 = <0x7>;
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ti,otap-del-sel-ddr50 = <0x4>;
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ti,otap-del-sel-ddr52 = <0x4>;
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ti,otap-del-sel-hs200 = <0x7>;
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ti,trm-icp = <0x8>;
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};
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};
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&cbass_mcu {
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u-boot,dm-spl;
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mcu_navss {
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u-boot,dm-spl;
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ringacc@2b800000 {
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u-boot,dm-spl;
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};
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dma-controller@285c0000 {
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u-boot,dm-spl;
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};
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};
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};
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&cbass_wakeup {
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u-boot,dm-spl;
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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wkup_i2c0_pins_default {
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u-boot,dm-spl;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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main_uart0_pins_default: main_uart0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
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AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
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AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
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AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
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>;
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u-boot,dm-spl;
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};
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main_mmc0_pins_default: main_mmc0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
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AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
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AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
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AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
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AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
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AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
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AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
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AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
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AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
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AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
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AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
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AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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u-boot,dm-spl;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
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AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
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AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
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AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
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AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
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AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
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AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
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AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
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>;
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u-boot,dm-spl;
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};
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usb0_pins_default: usb0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
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>;
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u-boot,dm-spl;
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};
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};
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&main_pmx1 {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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mcu_cpsw_pins_default: mcu_cpsw_pins_default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
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AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
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AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
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AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
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AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
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AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
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AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
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AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
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AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
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AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
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AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
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AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
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>;
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};
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mcu_mdio_pins_default: mcu_mdio1_pins_default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
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AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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>;
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};
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mcu-fss0-ospi0-pins-default {
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u-boot,dm-spl;
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};
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};
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&main_uart0 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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};
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&sdhci0 {
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u-boot,dm-spl;
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};
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&sdhci1 {
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u-boot,dm-spl;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc1_pins_default>;
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sdhci-caps-mask = <0x7 0x0>;
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ti,driver-strength-ohm = <50>;
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};
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&mcu_cpsw {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
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};
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&davinci_mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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};
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&mcu_cpsw {
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reg = <0x0 0x46000000 0x0 0x200000>,
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<0x0 0x40f00200 0x0 0x2>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@40f04040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg= <0x0 0x40f04040 0x0 0x4>;
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reg-names = "gmii-sel";
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};
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};
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&wkup_i2c0 {
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u-boot,dm-spl;
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};
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&usb1 {
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dr_mode = "peripheral";
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};
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&fss {
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u-boot,dm-spl;
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};
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&ospi0 {
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u-boot,dm-spl;
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flash@0{
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u-boot,dm-spl;
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};
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};
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&chipid {
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u-boot,dm-spl;
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};
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&dwc3_0 {
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status = "okay";
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u-boot,dm-spl;
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};
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&usb0_phy {
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status = "okay";
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u-boot,dm-spl;
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};
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&usb0 {
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pinctrl-names = "default";
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pinctrl-0 = <&usb0_pins_default>;
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dr_mode = "host";
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u-boot,dm-spl;
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};
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&scm_conf {
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u-boot,dm-spl;
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};
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