mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
d751b0c000
This syncs the rk3328 clock header file from Linux kernel next-20200324,
to support newer hardware blocks when syncing the device tree files.
The last non-merge commit to touch it was
0dc14b013f79 ("clk: rockchip: add clock id for watchdog pclk on rk3328")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
393 lines
9.2 KiB
C
393 lines
9.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
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* Author: Elaine <zhangqing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define PLL_NPLL 5
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#define ARMCLK 6
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/* sclk gates (special clocks) */
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#define SCLK_RTC32K 30
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#define SCLK_SDMMC_EXT 31
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#define SCLK_SPI 32
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#define SCLK_SDMMC 33
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#define SCLK_SDIO 34
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#define SCLK_EMMC 35
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#define SCLK_TSADC 36
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#define SCLK_SARADC 37
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#define SCLK_UART0 38
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#define SCLK_UART1 39
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#define SCLK_UART2 40
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#define SCLK_I2S0 41
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#define SCLK_I2S1 42
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#define SCLK_I2S2 43
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#define SCLK_I2S1_OUT 44
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#define SCLK_I2S2_OUT 45
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#define SCLK_SPDIF 46
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#define SCLK_TIMER0 47
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#define SCLK_TIMER1 48
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#define SCLK_TIMER2 49
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#define SCLK_TIMER3 50
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#define SCLK_TIMER4 51
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#define SCLK_TIMER5 52
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#define SCLK_WIFI 53
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#define SCLK_CIF_OUT 54
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#define SCLK_I2C0 55
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#define SCLK_I2C1 56
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#define SCLK_I2C2 57
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#define SCLK_I2C3 58
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#define SCLK_CRYPTO 59
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#define SCLK_PWM 60
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#define SCLK_PDM 61
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#define SCLK_EFUSE 62
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#define SCLK_OTP 63
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#define SCLK_DDRCLK 64
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#define SCLK_VDEC_CABAC 65
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#define SCLK_VDEC_CORE 66
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#define SCLK_VENC_DSP 67
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#define SCLK_VENC_CORE 68
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#define SCLK_RGA 69
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#define SCLK_HDMI_SFC 70
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#define SCLK_HDMI_CEC 71
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#define SCLK_USB3_REF 72
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#define SCLK_USB3_SUSPEND 73
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#define SCLK_SDMMC_DRV 74
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#define SCLK_SDIO_DRV 75
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#define SCLK_EMMC_DRV 76
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#define SCLK_SDMMC_EXT_DRV 77
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#define SCLK_SDMMC_SAMPLE 78
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#define SCLK_SDIO_SAMPLE 79
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#define SCLK_EMMC_SAMPLE 80
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#define SCLK_SDMMC_EXT_SAMPLE 81
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#define SCLK_VOP 82
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#define SCLK_MAC2PHY_RXTX 83
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#define SCLK_MAC2PHY_SRC 84
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#define SCLK_MAC2PHY_REF 85
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#define SCLK_MAC2PHY_OUT 86
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#define SCLK_MAC2IO_RX 87
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#define SCLK_MAC2IO_TX 88
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#define SCLK_MAC2IO_REFOUT 89
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#define SCLK_MAC2IO_REF 90
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#define SCLK_MAC2IO_OUT 91
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#define SCLK_TSP 92
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#define SCLK_HSADC_TSP 93
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#define SCLK_USB3PHY_REF 94
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#define SCLK_REF_USB3OTG 95
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#define SCLK_USB3OTG_REF 96
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#define SCLK_USB3OTG_SUSPEND 97
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#define SCLK_REF_USB3OTG_SRC 98
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#define SCLK_MAC2IO_SRC 99
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#define SCLK_MAC2IO 100
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#define SCLK_MAC2PHY 101
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#define SCLK_MAC2IO_EXT 102
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/* dclk gates */
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#define DCLK_LCDC 120
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#define DCLK_HDMIPHY 121
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#define HDMIPHY 122
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#define USB480M 123
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#define DCLK_LCDC_SRC 124
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/* aclk gates */
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#define ACLK_AXISRAM 130
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#define ACLK_VOP_PRE 131
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#define ACLK_USB3OTG 132
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#define ACLK_RGA_PRE 133
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#define ACLK_DMAC 134
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#define ACLK_GPU 135
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#define ACLK_BUS_PRE 136
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#define ACLK_PERI_PRE 137
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#define ACLK_RKVDEC_PRE 138
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#define ACLK_RKVDEC 139
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#define ACLK_RKVENC 140
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#define ACLK_VPU_PRE 141
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#define ACLK_VIO_PRE 142
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#define ACLK_VPU 143
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#define ACLK_VIO 144
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#define ACLK_VOP 145
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#define ACLK_GMAC 146
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#define ACLK_H265 147
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#define ACLK_H264 148
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#define ACLK_MAC2PHY 149
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#define ACLK_MAC2IO 150
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#define ACLK_DCF 151
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#define ACLK_TSP 152
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#define ACLK_PERI 153
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#define ACLK_RGA 154
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#define ACLK_IEP 155
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#define ACLK_CIF 156
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#define ACLK_HDCP 157
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/* pclk gates */
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#define PCLK_GPIO0 200
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#define PCLK_GPIO1 201
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#define PCLK_GPIO2 202
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#define PCLK_GPIO3 203
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#define PCLK_GRF 204
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#define PCLK_I2C0 205
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#define PCLK_I2C1 206
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#define PCLK_I2C2 207
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#define PCLK_I2C3 208
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#define PCLK_SPI 209
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#define PCLK_UART0 210
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#define PCLK_UART1 211
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#define PCLK_UART2 212
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#define PCLK_TSADC 213
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#define PCLK_PWM 214
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#define PCLK_TIMER 215
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#define PCLK_BUS_PRE 216
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#define PCLK_PERI_PRE 217
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#define PCLK_HDMI_CTRL 218
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#define PCLK_HDMI_PHY 219
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#define PCLK_GMAC 220
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#define PCLK_H265 221
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#define PCLK_MAC2PHY 222
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#define PCLK_MAC2IO 223
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#define PCLK_USB3PHY_OTG 224
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#define PCLK_USB3PHY_PIPE 225
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#define PCLK_USB3_GRF 226
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#define PCLK_USB2_GRF 227
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#define PCLK_HDMIPHY 228
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#define PCLK_DDR 229
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#define PCLK_PERI 230
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#define PCLK_HDMI 231
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#define PCLK_HDCP 232
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#define PCLK_DCF 233
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#define PCLK_SARADC 234
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#define PCLK_ACODECPHY 235
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#define PCLK_WDT 236
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/* hclk gates */
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#define HCLK_PERI 308
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#define HCLK_TSP 309
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#define HCLK_GMAC 310
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#define HCLK_I2S0_8CH 311
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#define HCLK_I2S1_8CH 312
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#define HCLK_I2S2_2CH 313
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#define HCLK_SPDIF_8CH 314
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#define HCLK_VOP 315
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#define HCLK_NANDC 316
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#define HCLK_SDMMC 317
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#define HCLK_SDIO 318
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#define HCLK_EMMC 319
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#define HCLK_SDMMC_EXT 320
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#define HCLK_RKVDEC_PRE 321
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#define HCLK_RKVDEC 322
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#define HCLK_RKVENC 323
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#define HCLK_VPU_PRE 324
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#define HCLK_VIO_PRE 325
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#define HCLK_VPU 326
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#define HCLK_BUS_PRE 328
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#define HCLK_PERI_PRE 329
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#define HCLK_H264 330
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#define HCLK_CIF 331
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#define HCLK_OTG_PMU 332
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#define HCLK_OTG 333
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#define HCLK_HOST0 334
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#define HCLK_HOST0_ARB 335
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#define HCLK_CRYPTO_MST 336
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#define HCLK_CRYPTO_SLV 337
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#define HCLK_PDM 338
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#define HCLK_IEP 339
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#define HCLK_RGA 340
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#define HCLK_HDCP 341
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#define CLK_NR_CLKS (HCLK_HDCP + 1)
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/* soft-reset indices */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE2_PO 2
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#define SRST_CORE3_PO 3
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#define SRST_CORE0 4
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#define SRST_CORE1 5
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#define SRST_CORE2 6
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#define SRST_CORE3 7
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#define SRST_CORE0_DBG 8
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#define SRST_CORE1_DBG 9
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#define SRST_CORE2_DBG 10
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#define SRST_CORE3_DBG 11
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#define SRST_TOPDBG 12
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#define SRST_CORE_NIU 13
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#define SRST_STRC_A 14
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#define SRST_L2C 15
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#define SRST_A53_GIC 18
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#define SRST_DAP 19
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#define SRST_PMU_P 21
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#define SRST_EFUSE 22
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#define SRST_BUSSYS_H 23
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#define SRST_BUSSYS_P 24
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#define SRST_SPDIF 25
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#define SRST_INTMEM 26
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#define SRST_ROM 27
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#define SRST_GPIO0 28
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#define SRST_GPIO1 29
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#define SRST_GPIO2 30
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#define SRST_GPIO3 31
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#define SRST_I2S0 32
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#define SRST_I2S1 33
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#define SRST_I2S2 34
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#define SRST_I2S0_H 35
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#define SRST_I2S1_H 36
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#define SRST_I2S2_H 37
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#define SRST_UART0 38
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#define SRST_UART1 39
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#define SRST_UART2 40
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#define SRST_UART0_P 41
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#define SRST_UART1_P 42
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#define SRST_UART2_P 43
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#define SRST_I2C0 44
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#define SRST_I2C1 45
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#define SRST_I2C2 46
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#define SRST_I2C3 47
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#define SRST_I2C0_P 48
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#define SRST_I2C1_P 49
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#define SRST_I2C2_P 50
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#define SRST_I2C3_P 51
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#define SRST_EFUSE_SE_P 52
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#define SRST_EFUSE_NS_P 53
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#define SRST_PWM0 54
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#define SRST_PWM0_P 55
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#define SRST_DMA 56
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#define SRST_TSP_A 57
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#define SRST_TSP_H 58
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#define SRST_TSP 59
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#define SRST_TSP_HSADC 60
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#define SRST_DCF_A 61
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#define SRST_DCF_P 62
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#define SRST_SCR 64
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#define SRST_SPI 65
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#define SRST_TSADC 66
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#define SRST_TSADC_P 67
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#define SRST_CRYPTO 68
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#define SRST_SGRF 69
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#define SRST_GRF 70
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#define SRST_USB_GRF 71
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#define SRST_TIMER_6CH_P 72
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#define SRST_TIMER0 73
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#define SRST_TIMER1 74
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#define SRST_TIMER2 75
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#define SRST_TIMER3 76
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#define SRST_TIMER4 77
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#define SRST_TIMER5 78
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#define SRST_USB3GRF 79
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#define SRST_PHYNIU 80
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#define SRST_HDMIPHY 81
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#define SRST_VDAC 82
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#define SRST_ACODEC_p 83
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#define SRST_SARADC 85
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#define SRST_SARADC_P 86
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#define SRST_GRF_DDR 87
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#define SRST_DFIMON 88
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#define SRST_MSCH 89
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#define SRST_DDRMSCH 91
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#define SRST_DDRCTRL 92
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#define SRST_DDRCTRL_P 93
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#define SRST_DDRPHY 94
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#define SRST_DDRPHY_P 95
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#define SRST_GMAC_NIU_A 96
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#define SRST_GMAC_NIU_P 97
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#define SRST_GMAC2PHY_A 98
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#define SRST_GMAC2IO_A 99
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#define SRST_MACPHY 100
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#define SRST_OTP_PHY 101
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#define SRST_GPU_A 102
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#define SRST_GPU_NIU_A 103
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#define SRST_SDMMCEXT 104
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#define SRST_PERIPH_NIU_A 105
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#define SRST_PERIHP_NIU_H 106
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#define SRST_PERIHP_P 107
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#define SRST_PERIPHSYS_H 108
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#define SRST_MMC0 109
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#define SRST_SDIO 110
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#define SRST_EMMC 111
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#define SRST_USB2OTG_H 112
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#define SRST_USB2OTG 113
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#define SRST_USB2OTG_ADP 114
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#define SRST_USB2HOST_H 115
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#define SRST_USB2HOST_ARB 116
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#define SRST_USB2HOST_AUX 117
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#define SRST_USB2HOST_EHCIPHY 118
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#define SRST_USB2HOST_UTMI 119
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#define SRST_USB3OTG 120
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#define SRST_USBPOR 121
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#define SRST_USB2OTG_UTMI 122
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#define SRST_USB2HOST_PHY_UTMI 123
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#define SRST_USB3OTG_UTMI 124
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#define SRST_USB3PHY_U2 125
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#define SRST_USB3PHY_U3 126
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#define SRST_USB3PHY_PIPE 127
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#define SRST_VIO_A 128
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#define SRST_VIO_BUS_H 129
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#define SRST_VIO_H2P_H 130
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#define SRST_VIO_ARBI_H 131
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#define SRST_VOP_NIU_A 132
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#define SRST_VOP_A 133
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#define SRST_VOP_H 134
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#define SRST_VOP_D 135
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#define SRST_RGA 136
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#define SRST_RGA_NIU_A 137
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#define SRST_RGA_A 138
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#define SRST_RGA_H 139
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#define SRST_IEP_A 140
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#define SRST_IEP_H 141
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#define SRST_HDMI 142
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#define SRST_HDMI_P 143
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#define SRST_HDCP_A 144
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#define SRST_HDCP 145
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#define SRST_HDCP_H 146
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#define SRST_CIF_A 147
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#define SRST_CIF_H 148
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#define SRST_CIF_P 149
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#define SRST_OTP_P 150
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#define SRST_OTP_SBPI 151
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#define SRST_OTP_USER 152
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#define SRST_DDRCTRL_A 153
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#define SRST_DDRSTDY_P 154
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#define SRST_DDRSTDY 155
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#define SRST_PDM_H 156
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#define SRST_PDM 157
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#define SRST_USB3PHY_OTG_P 158
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#define SRST_USB3PHY_PIPE_P 159
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#define SRST_VCODEC_A 160
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#define SRST_VCODEC_NIU_A 161
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#define SRST_VCODEC_H 162
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#define SRST_VCODEC_NIU_H 163
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#define SRST_VDEC_A 164
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#define SRST_VDEC_NIU_A 165
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#define SRST_VDEC_H 166
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#define SRST_VDEC_NIU_H 167
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#define SRST_VDEC_CORE 168
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#define SRST_VDEC_CABAC 169
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#define SRST_DDRPHYDIV 175
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#define SRST_RKVENC_NIU_A 176
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#define SRST_RKVENC_NIU_H 177
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#define SRST_RKVENC_H265_A 178
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#define SRST_RKVENC_H265_P 179
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#define SRST_RKVENC_H265_CORE 180
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#define SRST_RKVENC_H265_DSP 181
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#define SRST_RKVENC_H264_A 182
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#define SRST_RKVENC_H264_H 183
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#define SRST_RKVENC_INTMEM 184
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#endif
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