mirror of
https://github.com/AsahiLinux/u-boot
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d1bbe1bedd
Add DTs for R8A779F0 S4 Spider CPU boards and Breakout boards.
Based on Linux next 20230228 DTs up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, update commit message]
105 lines
1.9 KiB
Text
105 lines
1.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Spider Ethernet sub-board
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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ð_serdes {
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status = "okay";
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};
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&i2c4 {
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eeprom@52 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "ethernet-sub-board";
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reg = <0x52>;
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pagesize = <8>;
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};
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};
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&pfc {
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tsn0_pins: tsn0 {
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groups = "tsn0_mdio_b", "tsn0_link_b";
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function = "tsn0";
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power-source = <1800>;
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};
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tsn1_pins: tsn1 {
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groups = "tsn1_mdio_b", "tsn1_link_b";
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function = "tsn1";
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power-source = <1800>;
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};
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tsn2_pins: tsn2 {
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groups = "tsn2_mdio_b", "tsn2_link_b";
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function = "tsn2";
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power-source = <1800>;
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};
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};
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&rswitch {
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pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
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pinctrl-names = "default";
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status = "okay";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phy-handle = <&u101>;
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phy-mode = "sgmii";
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phys = <ð_serdes 0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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u101: ethernet-phy@1 {
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reg = <1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupt-parent = <&gpio3>;
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interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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port@1 {
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reg = <1>;
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phy-handle = <&u201>;
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phy-mode = "sgmii";
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phys = <ð_serdes 1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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u201: ethernet-phy@2 {
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reg = <2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupt-parent = <&gpio3>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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port@2 {
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reg = <2>;
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phy-handle = <&u301>;
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phy-mode = "sgmii";
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phys = <ð_serdes 2>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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u301: ethernet-phy@3 {
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reg = <3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupt-parent = <&gpio3>;
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interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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};
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};
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