mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 03:08:31 +00:00
131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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static void flash__init (void);
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static void ether__init (void);
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static inline void delay (unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* arch number of OMAP 1510-Board */
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gd->bd->bi_arch_number = 234;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x10000100;
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/* kk - this speeds up your boot a quite a bit. However to make it
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* work, you need make sure your kernel startup flush bug is fixed.
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* ... rkw ...
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*/
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icache_enable ();
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flash__init ();
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ether__init ();
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return 0;
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}
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int misc_init_r (void)
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{
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/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
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/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
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/* setup gpio direction to match board (no floats!) */
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/**gdir = 0xCFF9; */
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/**mdir = 0x103F; */
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return (0);
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}
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/******************************
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Routine:
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Description:
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******************************/
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static void flash__init (void)
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{
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#define CS0_CHIP_SELECT_REG 0xfffecc10
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#define CS3_CHIP_SELECT_REG 0xfffecc1c
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#define EMIFS_GlB_Config_REG 0xfffecc0c
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{
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unsigned int regval;
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regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
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regval = regval | 0x0001; /* Turn off write protection for flash devices. */
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if (regval & 0x0002) {
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regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
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/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
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/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
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/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
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}
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*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
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}
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}
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/******************************
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Routine:
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Description:
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******************************/
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static void ether__init (void)
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{
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#define ETH_CONTROL_REG 0x0800000b
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/* take the Ethernet controller out of reset and wait
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* for the EEPROM load to complete.
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*/
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*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
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udelay (3);
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}
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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