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cce625e557
Set the PCI class code for JSE board as part of PCI interface setup * Patch by Michael Bendzick, 15 Jul 2004: Fix problem with writes with odd sizes in drivers/cfi_flash.c when CFG_FLASH_USE_BUFFER_WRITE is set
92 lines
3.5 KiB
C
92 lines
3.5 KiB
C
/*
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* Copyright (c) 2004 Picture Elements, Inc.
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* Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ident "$Id:$"
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# include <common.h>
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# include <pci.h>
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# include "jse_priv.h"
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/*
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* The JSE board has an Intel 21555 non-transparent bridge for
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* communication with the host. We need to render it harmless on the
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* JSE side, but leave it alone on the host (primary) side. Normally,
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* this will all be done before the host BIOS can gain access to the
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* board, due to the Primary Access Lockout bit.
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*
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* The host_bridge_init function is called as a late initialization
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* function, after most of the board is set up, including a PCI scan.
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*/
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void host_bridge_init (void)
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{
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/* The bridge chip is at a fixed location. */
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pci_dev_t dev = PCI_BDF (0, 10, 0);
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int rc;
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/* Set PCI Class code --
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The primary side sees this class code at 0x08 in the
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primary config space. This must be something other then a
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bridge, or MS Windows starts doing weird stuff to me. */
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pci_write_config_dword (dev, 0x48, 0x04800000);
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/* Set subsystem ID --
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The primary side sees this value at 0x2c. We set it here so
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that the host can tell what sort of device this is:
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We are a Picture Elements [0x12c5] JSE [0x008a]. */
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pci_write_config_dword (dev, 0x6c, 0x008a12c5);
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/* Downstream (Primary-to-Secondary) BARs are set up mostly
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off. We need only the Memory-0 Bar so that the host can get
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at the CSR region to set up tables and the lot. */
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/* Downstream Memory 0 setup (4K for CSR) */
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pci_write_config_dword (dev, 0xac, 0xfffff000);
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/* Downstream Memory 1 setup (off) */
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pci_write_config_dword (dev, 0xb0, 0x00000000);
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/* Downstream Memory 2 setup (off) */
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pci_write_config_dword (dev, 0xb4, 0x00000000);
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/* Downstream Memory 3 setup (off) */
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pci_write_config_dword (dev, 0xb8, 0x00000000);
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/* Upstream (Secondary-to-Primary) BARs are used to get at
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host memory from the JSE card. Create two regions: a small
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one to manage individual word reads/writes, and a larger
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one for doing bulk frame moves. */
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/* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
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pci_write_config_dword (dev, 0xc4, 0xfffff000);
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/* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
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pci_write_config_dword (dev, 0xc8, 0xfffff000);
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/* Upstream Memory 2 (BAR4) uses page translation, and is set
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up in CCR1. Configure for 4K pages. */
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/* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
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bit as well, so we are done configuring after this
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point. Therefore, this must be the last step.
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CC1[15:12]= 0 (disable I2O message unit)
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CC1[11:8] = 0x5 (4K page size)
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CC0[11] = 1 (Secondary Clock Disable: disable clock)
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CC0[10] = 0 (Primary Access Lockout: allow primary access)
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*/
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pci_write_config_dword (dev, 0xcc, 0x05000800);
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}
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