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323 lines
10 KiB
C
323 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _SYS_ENV_LIB_H
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#define _SYS_ENV_LIB_H
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#include "../../../drivers/ddr/marvell/a38x/ddr3_init.h"
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/* Serdes definitions */
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#define COMMON_PHY_BASE_ADDR 0x18300
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#define DEVICE_CONFIGURATION_REG0 0x18284
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#define DEVICE_CONFIGURATION_REG1 0x18288
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#define COMMON_PHY_CONFIGURATION1_REG 0x18300
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#define COMMON_PHY_CONFIGURATION2_REG 0x18304
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#define COMMON_PHY_CONFIGURATION4_REG 0x1830c
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#define COMMON_PHY_STATUS1_REG 0x18318
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#define COMMON_PHYS_SELECTORS_REG 0x183fc
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#define SOC_CONTROL_REG1 0x18204
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#define GENERAL_PURPOSE_RESERVED0_REG 0x182e0
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#define GBE_CONFIGURATION_REG 0x18460
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#define DEVICE_SAMPLE_AT_RESET1_REG 0x18600
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#define DEVICE_SAMPLE_AT_RESET2_REG 0x18604
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#define DEV_ID_REG 0x18238
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#define CORE_PLL_PARAMETERS_REG 0xe42e0
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#define CORE_PLL_CONFIG_REG 0xe42e4
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#define QSGMII_CONTROL_REG1 0x18494
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#define DEV_ID_REG_DEVICE_ID_OFFS 16
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#define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
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#define SAR_FREQ_OFFSET 10
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#define SAR_FREQ_MASK 0x1f
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#define SAR_DEV_ID_OFFS 27
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#define SAR_DEV_ID_MASK 0x7
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#define POWER_AND_PLL_CTRL_REG 0xa0004
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#define CALIBRATION_CTRL_REG 0xa0008
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#define DFE_REG0 0xa001c
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#define DFE_REG3 0xa0028
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#define RESET_DFE_REG 0xa0148
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#define LOOPBACK_REG 0xa008c
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#define SYNC_PATTERN_REG 0xa0090
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#define INTERFACE_REG 0xa0094
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#define ISOLATE_REG 0xa0098
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#define MISC_REG 0xa013c
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#define GLUE_REG 0xa0140
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#define GENERATION_DIVIDER_FORCE_REG 0xa0144
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#define PLLINTP_REG1 0xa0150
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#define PCIE_REG0 0xa0120
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#define LANE_ALIGN_REG0 0xa0124
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#define SQUELCH_FFE_SETTING_REG 0xa0018
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#define G1_SETTINGS_0_REG 0xa0034
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#define G1_SETTINGS_1_REG 0xa0038
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#define G1_SETTINGS_3_REG 0xa0440
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#define G1_SETTINGS_4_REG 0xa0444
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#define G2_SETTINGS_0_REG 0xa003c
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#define G2_SETTINGS_1_REG 0xa0040
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#define G2_SETTINGS_2_REG 0xa00f8
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#define G2_SETTINGS_3_REG 0xa0448
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#define G2_SETTINGS_4_REG 0xa044c
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#define G3_SETTINGS_0_REG 0xa0044
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#define G3_SETTINGS_1_REG 0xa0048
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#define G3_SETTINGS_3_REG 0xa0450
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#define G3_SETTINGS_4_REG 0xa0454
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#define VTHIMPCAL_CTRL_REG 0xa0104
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#define REF_REG0 0xa0134
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#define CAL_REG6 0xa0168
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#define RX_REG2 0xa0184
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#define RX_REG3 0xa0188
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#define PCIE_REG1 0xa0288
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#define PCIE_REG3 0xa0290
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#define LANE_CFG0_REG 0xa0600
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#define LANE_CFG1_REG 0xa0604
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#define LANE_CFG4_REG 0xa0620
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#define LANE_CFG5_REG 0xa0624
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#define GLOBAL_CLK_CTRL 0xa0704
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#define GLOBAL_TEST_CTRL 0xa0708
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#define GLOBAL_MISC_CTRL 0xa0718
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#define GLOBAL_CLK_SRC_HI 0xa0710
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#define GLOBAL_CLK_CTRL 0xa0704
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#define GLOBAL_MISC_CTRL 0xa0718
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#define GLOBAL_PM_CTRL 0xa0740
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/* SATA registers */
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#define SATA_CTRL_REG_IND_ADDR 0xa80a0
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#define SATA_CTRL_REG_IND_DATA 0xa80a4
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#define SATA_VENDOR_PORT_0_REG_ADDR 0xa8178
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#define SATA_VENDOR_PORT_1_REG_ADDR 0xa81f8
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#define SATA_VENDOR_PORT_0_REG_DATA 0xa817c
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#define SATA_VENDOR_PORT_1_REG_DATA 0xa81fc
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/* Reference clock values and mask */
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#define POWER_AND_PLL_CTRL_REG_100MHZ_VAL 0x0
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#define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1 0x1
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#define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2 0x2
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#define POWER_AND_PLL_CTRL_REG_40MHZ_VAL 0x3
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#define GLOBAL_PM_CTRL_REG_25MHZ_VAL 0x7
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#define GLOBAL_PM_CTRL_REG_40MHZ_VAL 0xc
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#define LANE_CFG4_REG_25MHZ_VAL 0x200
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#define LANE_CFG4_REG_40MHZ_VAL 0x300
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#define POWER_AND_PLL_CTRL_REG_MASK (~(0x1f))
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#define GLOBAL_PM_CTRL_REG_MASK (~(0xff))
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#define LANE_CFG4_REG_MASK (~(0x1f00))
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#define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1
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#define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1
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#define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1
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#define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1
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#define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1)
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#define MAX_SELECTOR_VAL 10
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/* TWSI addresses */
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/* starting from A38x A0, i2c address of EEPROM is 0x57 */
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#define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \
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MV_88F68XX_Z1_ID ? 0x50 : 0x57)
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#define RD_GET_MODE_ADDR 0x4c
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#define DB_GET_MODE_SLM1363_ADDR 0x25
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#define DB_GET_MODE_SLM1364_ADDR 0x24
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#define DB381_GET_MODE_SLM1426_1427_ADDR 0x56
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/* DB-BP Board 'SatR' mapping */
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#define SATR_DB_LANE1_MAX_OPTIONS 7
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#define SATR_DB_LANE1_CFG_MASK 0x7
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#define SATR_DB_LANE1_CFG_OFFSET 0
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#define SATR_DB_LANE2_MAX_OPTIONS 4
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#define SATR_DB_LANE2_CFG_MASK 0x38
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#define SATR_DB_LANE2_CFG_OFFSET 3
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/* GP Board 'SatR' mapping */
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#define SATR_GP_LANE1_CFG_MASK 0x4
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#define SATR_GP_LANE1_CFG_OFFSET 2
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#define SATR_GP_LANE2_CFG_MASK 0x8
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#define SATR_GP_LANE2_CFG_OFFSET 3
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/* For setting MPP2 and MPP3 to be TWSI mode and MPP 0,1 to UART mode */
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#define MPP_CTRL_REG 0x18000
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#define MPP_SET_MASK (~(0xffff))
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#define MPP_SET_DATA (0x1111)
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#define MPP_UART1_SET_MASK (~(0xff000))
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#define MPP_UART1_SET_DATA (0x66000)
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#define DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS 0
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/* DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS: Since address completion in 14bit
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* address mode, and given that [14:8] => [19:13], the 2 lower bits [9:8] =>
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* [14:13] are dismissed. hence field offset is also shifted to 10
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*/
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#define DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS 10
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#define RTC_MEMORY_CTRL_REG_BASE 0xE6000
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#define RTC_MEMORY_WRAPPER_COUNT 8
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#define RTC_MEMORY_WRAPPER_REG(i) (RTC_MEMORY_CTRL_REG_BASE + ((i) * 0x40))
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#define RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS 6
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#define RTC_MEMORY_WRAPPER_CTRL_VAL (0x1 << RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS)
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#define AVS_DEBUG_CNTR_REG 0xe4124
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#define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073
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#define AVS_ENABLED_CONTROL 0xe4130
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#define AVS_LOW_VDD_LIMIT_OFFS 4
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#define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS)
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#define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS)
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#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
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#define AVS_HIGH_VDD_LIMIT_OFFS 12
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#define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS)
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#define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS)
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#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
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/* Board ID numbers */
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#define MARVELL_BOARD_ID_MASK 0x10
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/* Customer boards for A38x */
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#define A38X_CUSTOMER_BOARD_ID_BASE 0x0
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#define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0)
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#define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1)
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#define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2)
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#define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \
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A38X_CUSTOMER_BOARD_ID_BASE)
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/* Marvell boards for A38x */
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#define A38X_MARVELL_BOARD_ID_BASE 0x10
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#define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0)
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#define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1)
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#define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2)
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#define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3)
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#define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4)
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#define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5)
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#define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6)
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#define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7)
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#define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \
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A38X_MARVELL_BOARD_ID_BASE)
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#define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE
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#define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0
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#define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1
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#define MV_MAX_CUSTOMER_BOARD_ID A38X_MV_MAX_CUSTOMER_BOARD_ID
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#define MV_CUSTOMER_BOARD_NUM A38X_MV_CUSTOMER_BOARD_NUM
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#define MARVELL_BOARD_ID_BASE A38X_MARVELL_BOARD_ID_BASE
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#define MV_MAX_MARVELL_BOARD_ID A38X_MV_MAX_MARVELL_BOARD_ID
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#define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM
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#define MV_DEFAULT_BOARD_ID DB_68XX_ID
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#define MV_DEFAULT_DEVICE_ID MV_6811
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#define MV_INVALID_BOARD_ID 0xffffffff
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/* device revesion */
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#define DEV_VERSION_ID_REG 0x1823c
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#define REVISON_ID_OFFS 8
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#define REVISON_ID_MASK 0xf00
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/* A38x revisions */
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#define MV_88F68XX_Z1_ID 0x0
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#define MV_88F68XX_A0_ID 0x4
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#define MV_88F68XX_B0_ID 0xa
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#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
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#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
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#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
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#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
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#define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40))
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#define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8)
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#define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \
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(MPP_REG_NUM(GPIO_NUM) * 8)));
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#define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32)
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#define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32)
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/* device ID */
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/* Armada 38x Family */
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#define MV_6810_DEV_ID 0x6810
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#define MV_6811_DEV_ID 0x6811
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#define MV_6820_DEV_ID 0x6820
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#define MV_6828_DEV_ID 0x6828
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enum {
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MV_6810,
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MV_6820,
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MV_6811,
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MV_6828,
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};
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#define MV_6820_INDEX 0
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#define MV_6810_INDEX 1
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#define MV_6811_INDEX 2
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#define MV_6828_INDEX 3
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#define MAX_DEV_ID_NUM 4
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#define MV_6820_INDEX 0
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#define MV_6810_INDEX 1
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#define MV_6811_INDEX 2
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#define MV_6828_INDEX 3
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enum unit_id {
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PEX_UNIT_ID,
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ETH_GIG_UNIT_ID,
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USB3H_UNIT_ID,
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USB3D_UNIT_ID,
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SATA_UNIT_ID,
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QSGMII_UNIT_ID,
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XAUI_UNIT_ID,
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RXAUI_UNIT_ID,
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MAX_UNITS_ID
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};
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struct board_wakeup_gpio {
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u32 board_id;
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int gpio_num;
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};
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enum suspend_wakeup_status {
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SUSPEND_WAKEUP_DISABLED,
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SUSPEND_WAKEUP_ENABLED,
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SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED,
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};
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/*
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* GPIO status indication for Suspend Wakeup:
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* If suspend to RAM is supported and GPIO inidcation is implemented,
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* set the gpio number
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* If suspend to RAM is supported but GPIO indication is not implemented
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* set '-2'
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* If suspend to RAM is not supported set '-1'
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*/
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#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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{A38X_CUSTOMER_BOARD_ID0, -1 }, \
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{A38X_CUSTOMER_BOARD_ID0, -1 }, \
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};
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#else
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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{RD_NAS_68XX_ID, -2 }, \
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{DB_68XX_ID, -1 }, \
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{RD_AP_68XX_ID, -2 }, \
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{DB_AP_68XX_ID, -2 }, \
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{DB_GP_68XX_ID, -2 }, \
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{DB_BP_6821_ID, -2 }, \
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{DB_AMC_6820_ID, -2 }, \
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};
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#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
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u32 mv_board_tclk_get(void);
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u32 mv_board_id_get(void);
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u32 mv_board_id_index_get(u32 board_id);
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u32 sys_env_unit_max_num_get(enum unit_id unit);
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enum suspend_wakeup_status sys_env_suspend_wakeup_check(void);
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u8 sys_env_device_rev_get(void);
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u32 sys_env_device_id_get(void);
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u16 sys_env_model_get(void);
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struct dlb_config *sys_env_dlb_config_ptr_get(void);
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u32 sys_env_get_cs_ena_from_reg(void);
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#endif /* _SYS_ENV_LIB_H */
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