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fe4a967575
Future gdsys boards will switch from the legacy drivers in board/gdsys/common to DM-based drivers. Define a Kconfig option that disables the legacy drivers. Signed-off-by: Mario Six <mario.six@gdsys.cc>
180 lines
4.3 KiB
C
180 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*/
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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#include <common.h>
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#include <i2c.h>
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#define ADV7611_I2C_ADDR 0x4c
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#define ADV7611_RDINFO 0x2051
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/*
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* ADV7611 I2C Addresses in u-boot notation
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*/
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enum {
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CP_I2C_ADDR = 0x22,
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DPLL_I2C_ADDR = 0x26,
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KSV_I2C_ADDR = 0x32,
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HDMI_I2C_ADDR = 0x34,
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EDID_I2C_ADDR = 0x36,
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INFOFRAME_I2C_ADDR = 0x3e,
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CEC_I2C_ADDR = 0x40,
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IO_I2C_ADDR = ADV7611_I2C_ADDR,
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};
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/*
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* Global Control Registers
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*/
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enum {
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IO_RD_INFO_MSB = 0xea,
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IO_RD_INFO_LSB = 0xeb,
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IO_CEC_ADDR = 0xf4,
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IO_INFOFRAME_ADDR = 0xf5,
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IO_DPLL_ADDR = 0xf8,
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IO_KSV_ADDR = 0xf9,
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IO_EDID_ADDR = 0xfa,
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IO_HDMI_ADDR = 0xfb,
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IO_CP_ADDR = 0xfd,
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};
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int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C;
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int adv7611_probe(unsigned int screen)
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{
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int old_bus = i2c_get_bus_num();
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unsigned int rd_info;
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int res = 0;
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i2c_set_bus_num(adv7611_i2c[screen]);
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rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8)
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| i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB);
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if (rd_info != ADV7611_RDINFO) {
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res = -1;
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goto out;
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}
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/*
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* set I2C addresses to default values
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*/
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i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1);
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i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1);
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i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1);
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i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1);
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i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1);
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i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1);
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i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1);
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/*
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* do magic initialization sequence from
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* "ADV7611 Register Settings Recommendations Revision 1.5"
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* with most registers undocumented
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*/
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i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00);
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i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03);
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i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08);
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i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f);
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i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70);
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i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda);
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i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01);
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i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98);
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i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44);
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/*
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* IO_REG_02, default 0xf0
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*
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* INP_COLOR_SPACE (IO, Address 0x02[7:4])
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* default: 0b1111 auto
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* set to : 0b0001 force RGB (range 0 to 255) input
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*
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* RGB_OUT (IO, Address 0x02[1])
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* default: 0 YPbPr color space output
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* set to : 1 RGB color space output
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*/
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i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12);
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/*
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* IO_REG_03, default 0x00
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*
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* OP_FORMAT_SEL (IO, Address 0x03[7:0])
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* default: 0x00 8-bit SDR ITU-656 mode
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* set to : 0x40 24-bit 4:4:4 SDR mode
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*/
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i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40);
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/*
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* IO_REG_05, default 0x2c
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*
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* AVCODE_INSERT_EN (IO, Address 0x05[2])
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* default: 1 insert AV codes into data stream
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* set to : 0 do not insert AV codes into data stream
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*/
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i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28);
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/*
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* IO_REG_0C, default 0x62
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*
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* POWER_DOWN (IO, Address 0x0C[5])
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* default: 1 chip is powered down
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* set to : 0 chip is operational
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*/
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i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42);
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/*
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* IO_REG_15, default 0xbe
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*
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* TRI_SYNCS (IO, Address 0x15[3)
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* TRI_LLC (IO, Address 0x15[2])
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* TRI_PIX (IO, Address 0x15[1])
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* default: 1 video output pins are tristate
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* set to : 0 video output pins are active
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*/
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i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0);
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/*
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* HDMI_REGISTER_02H, default 0xff
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*
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* CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0])
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* default: 1 disable termination
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* set to : 0 enable termination
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* Future options are:
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* - use the chips automatic termination control
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* - set this manually on cable detect
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* but at the moment this seems a safe default.
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*/
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i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe);
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/*
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* HDMI_CP_CNTRL_1, default 0x01
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*
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* HDMI_FRUN_EN (CP, Address 0xBA[0])
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* default: 1 Enable the free run feature in HDMI mode
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* set to : 0 Disable the free run feature in HDMI mode
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*/
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i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00);
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/*
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* INT1_CONFIGURATION, default 0x20
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*
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* INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6])
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* default: 00 Interrupt signal is active for 4 Xtal periods
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* set to : 11 Active until cleared
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*
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* INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0])
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* default: 00 Open drain
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* set to : 10 Drives high when active
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*/
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i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2);
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out:
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i2c_set_bus_num(old_bus);
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return res;
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}
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#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
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