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aeaef07c51
TXC line is directly connected from the SoC to the KSZ9131 PHY. There is a transient state on this signal, before configuring it to RGMII, which leads to packet transmit being blocked. Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes the issue. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
202 lines
4.1 KiB
Text
202 lines
4.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* sama7g5ek.dts - Device Tree file for SAMA7G5 EK
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* SAMA7G5 Evaluation Kit
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*
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* Copyright (c) 2020, Microchip Technology Inc.
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* 2020, Eugen Hristev <eugen.hristev@microchip.com>
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* 2020, Claudiu Beznea <claudiu.beznea@microchip.com>
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*/
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/dts-v1/;
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#include "sama7g5.dtsi"
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#include "sama7g5-pinfunc.h"
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/ {
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model = "Microchip SAMA7G5 Evaluation Kit";
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compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7";
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aliases {
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serial0 = &uart0;
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i2c0 = &i2c1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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clocks {
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slow_xtal: slow_xtal {
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clock-frequency = <32768>;
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};
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main_xtal: main_xtal {
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clock-frequency = <24000000>;
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};
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};
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ahb {
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apb {
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sdmmc0: sdio-host@e1204000 {
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc0_cmd_data_default
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&pinctrl_sdmmc0_ck_rstn_ds_cd_default>;
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status = "okay";
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};
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sdmmc1: sdio-host@e1208000 {
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default
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&pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>;
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status = "okay";
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};
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uart0: serial@e1824200 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx3_default>;
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status = "okay";
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};
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};
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};
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};
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&flx1 {
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atmel,flexcom-mode = <3>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx1_default>;
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status = "okay";
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eeprom@52 {
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compatible = "microchip,24aa02e48";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom@53 {
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compatible = "microchip,24aa02e48";
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reg = <0x53>;
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pagesize = <16>;
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};
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};
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&gmac0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txc_default>;
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phy-mode = "rgmii-id";
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status = "okay";
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ethernet-phy@7 {
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reg = <0x7>;
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};
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};
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&gmac1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gmac1_default>;
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phy-mode = "rmii";
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status = "okay";
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ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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&pinctrl {
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pinctrl_flx1_default: flx1_default {
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pinmux = <PIN_PC9__FLEXCOM1_IO0>,
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<PIN_PC10__FLEXCOM1_IO1>;
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bias-disable;
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};
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pinctrl_flx3_default: flx3_default {
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pinmux = <PIN_PD16__FLEXCOM3_IO0>,
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<PIN_PD17__FLEXCOM3_IO1>;
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bias-disable;
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};
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pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default {
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pinmux = <PIN_PA1__SDMMC0_CMD>,
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<PIN_PA3__SDMMC0_DAT0>,
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<PIN_PA4__SDMMC0_DAT1>,
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<PIN_PA5__SDMMC0_DAT2>,
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<PIN_PA6__SDMMC0_DAT3>,
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<PIN_PA7__SDMMC0_DAT4>,
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<PIN_PA8__SDMMC0_DAT5>,
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<PIN_PA9__SDMMC0_DAT6>,
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<PIN_PA10__SDMMC0_DAT7>;
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bias-pull-up;
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};
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pinctrl_sdmmc0_ck_rstn_ds_cd_default: sdmmc0_ck_rstn_ds_cd_default {
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pinmux = <PIN_PA0__SDMMC0_CK>,
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<PIN_PA2__SDMMC0_RSTN>,
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<PIN_PA11__SDMMC0_DS>,
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<PIN_PA14__SDMMC0_CD>;
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bias-pull-up;
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};
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pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default {
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pinmux = <PIN_PB29__SDMMC1_CMD>,
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<PIN_PB31__SDMMC1_DAT0>,
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<PIN_PC0__SDMMC1_DAT1>,
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<PIN_PC1__SDMMC1_DAT2>,
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<PIN_PC2__SDMMC1_DAT3>;
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bias-pull-up;
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};
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pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default {
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pinmux = <PIN_PB30__SDMMC1_CK>,
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<PIN_PB28__SDMMC1_RSTN>,
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<PIN_PC5__SDMMC1_1V8SEL>,
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<PIN_PC4__SDMMC1_CD>;
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bias-pull-up;
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};
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pinctrl_gmac0_default: gmac0_default {
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pinmux = <PIN_PA16__G0_TX0>,
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<PIN_PA17__G0_TX1>,
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<PIN_PA26__G0_TX2>,
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<PIN_PA27__G0_TX3>,
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<PIN_PA19__G0_RX0>,
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<PIN_PA20__G0_RX1>,
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<PIN_PA28__G0_RX2>,
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<PIN_PA29__G0_RX3>,
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<PIN_PA15__G0_TXEN>,
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<PIN_PA30__G0_RXCK>,
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<PIN_PA18__G0_RXDV>,
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<PIN_PA22__G0_MDC>,
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<PIN_PA23__G0_MDIO>,
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<PIN_PA25__G0_125CK>;
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bias-disable;
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};
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pinctrl_gmac0_txc_default: gmac0_txc_default {
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pinmux = <PIN_PA24__G0_TXCK>;
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bias-pull-up;
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};
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pinctrl_gmac1_default: gmac1_default {
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pinmux = <PIN_PD30__G1_TXCK>,
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<PIN_PD22__G1_TX0>,
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<PIN_PD23__G1_TX1>,
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<PIN_PD21__G1_TXEN>,
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<PIN_PD25__G1_RX0>,
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<PIN_PD26__G1_RX1>,
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<PIN_PD27__G1_RXER>,
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<PIN_PD24__G1_RXDV>,
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<PIN_PD28__G1_MDC>,
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<PIN_PD29__G1_MDIO>;
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bias-disable;
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};
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};
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