mirror of
https://github.com/AsahiLinux/u-boot
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e8918bccd8
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3 SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
217 lines
3.4 KiB
Text
217 lines
3.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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ethernet0 = &cpsw_port1;
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};
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};
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&cbass_main{
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u-boot,dm-spl;
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};
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&cbass_mcu_wakeup {
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u-boot,dm-spl;
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timer1: timer@40400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x40400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <25000000>;
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u-boot,dm-spl;
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};
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mcu_navss {
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u-boot,dm-spl;
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ringacc@2b800000 {
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u-boot,dm-spl;
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};
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dma-controller@285c0000 {
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u-boot,dm-spl;
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};
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};
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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mcu_cpsw_pins_default: mcu_cpsw_pins_default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
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J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
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J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
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J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
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J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
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J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
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J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
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J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
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J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
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J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
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J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
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J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
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>;
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};
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mcu_mdio_pins_default: mcu_mdio1_pins_default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
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J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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>;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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};
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&main_uart0 {
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u-boot,dm-spl;
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};
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&mcu_uart0 {
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u-boot,dm-spl;
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};
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&main_sdhci0 {
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u-boot,dm-spl;
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};
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&main_sdhci1 {
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u-boot,dm-spl;
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};
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&main_usbss0_pins_default {
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u-boot,dm-spl;
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};
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&usbss0 {
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u-boot,dm-spl;
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ti,usb2-only;
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};
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&usb0 {
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dr_mode = "peripheral";
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u-boot,dm-spl;
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};
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&mcu_cpsw {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
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};
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&davinci_mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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};
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&mcu_cpsw {
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reg = <0x0 0x46000000 0x0 0x200000>,
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<0x0 0x40f00200 0x0 0x2>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@40f04040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg= <0x0 0x40f04040 0x0 0x4>;
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reg-names = "gmii-sel";
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};
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};
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&main_mmc1_pins_default {
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u-boot,dm-spl;
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};
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&wkup_i2c0_pins_default {
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u-boot,dm-spl;
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};
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&wkup_i2c0 {
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u-boot,dm-spl;
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};
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&main_i2c0 {
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u-boot,dm-spl;
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};
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&main_i2c0_pins_default {
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u-boot,dm-spl;
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};
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&exp2 {
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u-boot,dm-spl;
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};
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&mcu_fss0_ospi0_pins_default {
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u-boot,dm-spl;
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};
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&fss {
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u-boot,dm-spl;
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};
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&ospi0 {
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u-boot,dm-spl;
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flash@0 {
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u-boot,dm-spl;
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};
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};
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&ospi1 {
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u-boot,dm-spl;
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flash@0 {
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u-boot,dm-spl;
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};
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};
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&mcu_fss0_ospi1_pins_default {
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u-boot,dm-spl;
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};
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&chipid {
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u-boot,dm-spl;
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};
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