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85ad184b3b
Since the current dflush() implementation is know to have some problems (as seem on lwmon5 ECC init) this patch removes it completely and replaces it by using clean_dcache_range(). Tested on Katmai with ECC DIMM. Signed-off-by: Stefan Roese <sr@denx.de>
305 lines
8.6 KiB
C
305 lines
8.6 KiB
C
/*
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* (C) Copyright 2007
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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* (C) Copyright 2006
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* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
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*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debug output */
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#undef DEBUG
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <ppc440.h>
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void hcu_led_set(u32 value);
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void dcbz_area(u32 start_address, u32 num_bytes);
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#define DDR_DCR_BASE 0x10
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#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
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#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
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#define DDR0_01_INT_MASK_MASK 0x000000FF
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#define DDR0_00_INT_ACK_ALL 0x7F000000
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#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
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#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
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#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
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#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
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#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
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#define DDR0_22 0x16
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/* ECC */
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#define DDR0_22_CTRL_RAW_MASK 0x03000000
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#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */
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#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */
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#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/
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#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
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#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
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#define ECC_RAM 0x03267F0B
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#define NO_ECC_RAM 0x00267F0B
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#define HCU_HW_SDRAM_CONFIG_MASK 0x7
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
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/* disable caching on DDR2 */
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void board_add_ram_info(int use_default)
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{
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PPC4xx_SYS_INFO board_cfg;
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u32 val;
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mfsdram(DDR0_22, val);
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val &= DDR0_22_CTRL_RAW_MASK;
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switch (val) {
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case DDR0_22_CTRL_RAW_ECC_DISABLE:
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puts(" (ECC disabled");
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break;
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case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
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puts(" (ECC check only");
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break;
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case DDR0_22_CTRL_RAW_NO_ECC_RAM:
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puts(" (no ECC ram");
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break;
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case DDR0_22_CTRL_RAW_ECC_ENABLE:
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puts(" (ECC enabled");
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break;
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}
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get_sys_info(&board_cfg);
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printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
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mfsdram(DDR0_03, val);
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val = DDR0_03_CASLAT_DECODE(val);
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printf(", CL%d)", val);
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}
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/*--------------------------------------------------------------------
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* wait_for_dlllock.
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*--------------------------------------------------------------------*/
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static int wait_for_dlllock(void)
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{
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unsigned long val;
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int wait = 0;
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/* -----------------------------------------------------------+
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* Wait for the DCC master delay line to finish calibration
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_17);
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val = DDR0_17_DLLLOCKREG_UNLOCKED;
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_17_DLLLOCKREG_MASK) ==
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DDR0_17_DLLLOCKREG_LOCKED)
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/* dlllockreg bit on */
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return 0;
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else
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wait++;
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}
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debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
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debug("Waiting for dlllockreg bit to raise\n");
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return -1;
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}
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/***********************************************************************
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*
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* sdram_panic -- Panic if we cannot configure the sdram correctly
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*
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************************************************************************/
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void sdram_panic(const char *reason)
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{
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printf("\n%s: reason %s", __FUNCTION__, reason);
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hcu_led_set(0xff);
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while (1) {
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}
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/* Never return */
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}
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#ifdef CONFIG_DDR_ECC
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static void blank_string(int size)
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{
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int i;
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for (i=0; i<size; i++)
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putc('\b');
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for (i=0; i<size; i++)
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putc(' ');
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for (i=0; i<size; i++)
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putc('\b');
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}
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/*---------------------------------------------------------------------------+
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* program_ecc.
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*---------------------------------------------------------------------------*/
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static void program_ecc(unsigned long start_address, unsigned long num_bytes)
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{
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u32 val;
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char str[] = "ECC generation -";
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#if defined(CONFIG_PRAM)
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u32 *magicPtr;
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u32 magic;
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if ((mfspr(dbcr0) & 0x80000000) == 0) {
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/* only if no external debugger is alive!
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* Check whether vxWorks is using EDR logging, if yes zero
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* also PostMortem and user reserved memory
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*/
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magicPtr = (u32 *)(start_address + num_bytes -
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(CONFIG_PRAM*1024) + sizeof(u32));
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magic = in_be32(magicPtr);
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debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
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__FUNCTION__, CONFIG_PRAM,
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magicPtr, magic);
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if (magic == 0xbeefbabe) {
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printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
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num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
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}
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}
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#endif
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sync();
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puts(str);
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/* ECC bit set method for cached memory */
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/* Fast method, no noticeable delay */
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dcbz_area(start_address, num_bytes);
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/* Write modified dcache lines back to memory */
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clean_dcache_range(start_address, start_address + num_bytes);
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blank_string(strlen(str));
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/* Clear error status */
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mfsdram(DDR0_00, val);
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mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
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/*
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* Clear possible ECC errors
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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mtspr(mcsr, mfspr(mcsr));
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/* Set 'int_mask' parameter to functionnal value */
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mfsdram(DDR0_01, val);
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mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
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DDR0_01_INT_MASK_ALL_OFF));
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return;
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}
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#endif
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/***********************************************************************
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*
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* initdram -- 440EPx's DDR controller is a DENALI Core
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*
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************************************************************************/
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long int initdram (int board_type)
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{
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unsigned int dram_size = 0;
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mtsdram(DDR0_02, 0x00000000);
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/* Values must be kept in sync with Excel-table <<A0001492.>> ! */
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mtsdram(DDR0_00, 0x0000190A);
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mtsdram(DDR0_01, 0x01000000);
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mtsdram(DDR0_03, 0x02030602);
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mtsdram(DDR0_04, 0x0A020200);
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mtsdram(DDR0_05, 0x02020307);
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switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) {
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case 1:
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dram_size = 256 * 1024 * 1024 ;
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mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
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mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
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mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
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break;
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case 0:
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default:
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dram_size = 128 * 1024 * 1024 ;
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mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
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mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
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mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
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break;
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}
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mtsdram(DDR0_07, 0x00090100);
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/*
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* TCPD=200 cycles of clock input is required to lock the DLL.
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* CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
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*/
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mtsdram(DDR0_08, 0x02C80001);
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mtsdram(DDR0_09, 0x00011D5F);
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mtsdram(DDR0_10, 0x00000100);
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mtsdram(DDR0_12, 0x00000003);
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mtsdram(DDR0_14, 0x00000000);
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mtsdram(DDR0_17, 0x1D000000);
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mtsdram(DDR0_18, 0x1D1D1D1D);
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mtsdram(DDR0_19, 0x1D1D1D1D);
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mtsdram(DDR0_20, 0x0B0B0B0B);
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mtsdram(DDR0_21, 0x0B0B0B0B);
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#ifdef CONFIG_DDR_ECC
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mtsdram(DDR0_22, ECC_RAM);
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#else
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mtsdram(DDR0_22, NO_ECC_RAM);
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#endif
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mtsdram(DDR0_23, 0x00000000);
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mtsdram(DDR0_24, 0x01020001);
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mtsdram(DDR0_26, 0x2D930517);
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mtsdram(DDR0_27, 0x00008236);
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mtsdram(DDR0_28, 0x00000000);
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mtsdram(DDR0_31, 0x00000000);
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mtsdram(DDR0_42, 0x01000006);
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mtsdram(DDR0_44, 0x00000003);
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mtsdram(DDR0_02, 0x00000001);
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wait_for_dlllock();
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mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
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/*
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* Program tlb entries for this size (dynamic)
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*/
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remove_tlb(CFG_SDRAM_BASE, 256 << 20);
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program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
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/*
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* Setup 2nd TLB with same physical address but different virtual
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* address with cache enabled. This is done for fast ECC generation.
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*/
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program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
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#ifdef CONFIG_DDR_ECC
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/*
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* If ECC is enabled, initialize the parity bits.
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*/
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program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
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#endif
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return (dram_size);
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}
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