mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 10:52:09 +00:00
7262ff7e56
MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears incorrect. Without this delays in R5 SPL are 10x off. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
149 lines
2.2 KiB
Text
149 lines
2.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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serial0 = &wkup_uart0;
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serial1 = &mcu_uart0;
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serial2 = &main_uart8;
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i2c0 = &wkup_i2c0;
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i2c1 = &mcu_i2c0;
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i2c2 = &mcu_i2c1;
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i2c3 = &main_i2c0;
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ethernet0 = &cpsw_port1;
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};
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};
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&wkup_i2c0 {
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u-boot,dm-spl;
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};
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&cbass_main {
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u-boot,dm-spl;
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};
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&main_navss {
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u-boot,dm-spl;
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};
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&cbass_mcu_wakeup {
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u-boot,dm-spl;
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timer1: timer@40400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x40400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <250000000>;
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u-boot,dm-spl;
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};
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chipid@43000014 {
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u-boot,dm-spl;
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};
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};
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&mcu_navss {
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u-boot,dm-spl;
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};
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&mcu_ringacc {
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>,
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<0x0 0x28440000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
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u-boot,dm-spl;
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};
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&mcu_udmap {
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x284c0000 0x0 0x4000>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x284a0000 0x0 0x4000>,
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<0x0 0x2aa00000 0x0 0x40000>,
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<0x0 0x28400000 0x0 0x2000>;
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reg-names = "gcfg", "rchan", "rchanrt", "tchan",
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"tchanrt", "rflow";
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u-boot,dm-spl;
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&sms {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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};
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&main_uart8_pins_default {
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u-boot,dm-spl;
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};
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&main_mmc1_pins_default {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&main_uart8 {
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u-boot,dm-spl;
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};
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&mcu_uart0 {
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u-boot,dm-spl;
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};
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&wkup_uart0 {
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u-boot,dm-spl;
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};
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&mcu_cpsw {
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reg = <0x0 0x46000000 0x0 0x200000>,
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<0x0 0x40f00200 0x0 0x8>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@40f04040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg= <0x0 0x40f04040 0x0 0x4>;
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reg-names = "gmii-sel";
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};
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};
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&main_sdhci0 {
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u-boot,dm-spl;
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};
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&main_sdhci1 {
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u-boot,dm-spl;
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};
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