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https://github.com/AsahiLinux/u-boot
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90 lines
3 KiB
C
90 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration settings for the EXYNOS 78x0 based boards.
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*
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* Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
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* based on include/exynos7420-common.h
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* Copyright (C) 2016 Samsung Electronics
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* Thomas Abraham <thomas.ab@samsung.com>
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*/
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#ifndef __CONFIG_EXYNOS78x0_COMMON_H
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#define __CONFIG_EXYNOS78x0_COMMON_H
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/* High Level Configuration Options */
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#define CONFIG_SAMSUNG /* in a SAMSUNG core */
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#define CONFIG_S5P
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <linux/sizes.h>
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Timer input clock frequency */
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#define COUNTER_FREQUENCY 26000000
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#define CPU_RELEASE_ADDR secondary_boot_addr
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE)
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/* DRAM Memory Banks */
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#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
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#ifndef MEM_LAYOUT_ENV_SETTINGS
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"bootm_low=0x40000000\0"
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#endif
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#ifndef EXYNOS_DEVICE_SETTINGS
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#define EXYNOS_DEVICE_SETTINGS \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0"
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#endif
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#ifndef EXYNOS_FDTFILE_SETTING
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#define EXYNOS_FDTFILE_SETTING
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#endif
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#define EXTRA_ENV_SETTINGS \
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EXYNOS_DEVICE_SETTINGS \
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EXYNOS_FDTFILE_SETTING \
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MEM_LAYOUT_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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EXTRA_ENV_SETTINGS
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#endif /* __CONFIG_EXYNOS78x0_COMMON_H */
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